330 lines
12 KiB
Verilog
330 lines
12 KiB
Verilog
// Cache Memory (8way 4word) //
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// i_ means input port //
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// o_ means output port //
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// _p_ means data exchange with processor //
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// _m_ means data exchange with memory //
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// TO DO:
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// - Send in a response from memory of what the data is from the test bench
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`include "../VX_define.v"
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//`include "VX_priority_encoder.v"
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// `include "VX_Cache_Bank.v"
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//`include "cache_set.v"
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module VX_d_cache
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/*#(
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parameter CACHE_SIZE = 4096, // Bytes
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parameter CACHE_WAYS = 1,
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parameter CACHE_BLOCK = 128, // Bytes
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parameter CACHE_BANKS = 8,
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parameter NUM_REQ = 8
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)*/
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(
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clk,
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rst,
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i_p_addr,
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//i_p_byte_en,
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i_p_writedata,
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i_p_read_or_write, // 0 = Read | 1 = Write
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i_p_mem_read,
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i_p_mem_write,
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i_p_valid,
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//i_p_write,
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o_p_readdata,
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o_p_delay, // 0 = all threads done | 1 = Still threads that need to
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o_m_evict_addr,
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o_m_read_addr,
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o_m_writedata,
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o_m_read_or_write, // 0 = Read | 1 = Write
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o_m_valid,
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i_m_readdata,
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i_m_ready
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);
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//parameter NUMBER_BANKS = `CACHE_BANKS;
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//localparam NUM_WORDS_PER_BLOCK = `CACHE_BLOCK / (`CACHE_BANKS*4);
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//localparam CACHE_BLOCK_PER_BANK = (`CACHE_BLOCK / `CACHE_BANKS);
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localparam CACHE_IDLE = 0; // Idle
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localparam SEND_MEM_REQ = 1; // Write back this block into memory
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localparam RECIV_MEM_RSP = 2;
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//parameter cache_entry = 9;
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input wire clk, rst;
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input wire [`DCACHE_NUM_REQ-1:0] i_p_valid;
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input wire [`DCACHE_NUM_REQ-1:0][31:0] i_p_addr; // FIXME
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input wire [`DCACHE_NUM_REQ-1:0][31:0] i_p_writedata;
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input wire i_p_read_or_write; //, i_p_write;
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output reg [`DCACHE_NUM_REQ-1:0][31:0] o_p_readdata;
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output wire o_p_delay;
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output reg [31:0] o_m_evict_addr; // Address is xxxxxxxxxxoooobbbyy
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output reg [31:0] o_m_read_addr;
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output reg o_m_valid;
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output reg[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata;
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output reg o_m_read_or_write; //, o_m_write;
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input wire[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
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input wire i_m_ready;
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input wire[2:0] i_p_mem_read;
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input wire[2:0] i_p_mem_write;
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// Buffer for final data
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reg [`DCACHE_NUM_REQ-1:0][31:0] final_data_read;
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reg [`DCACHE_NUM_REQ-1:0][31:0] new_final_data_read;
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wire[`DCACHE_NUM_REQ-1:0][31:0] new_final_data_read_Qual;
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assign o_p_readdata = new_final_data_read_Qual;
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wire[`DCACHE_BANKS - 1 : 0][`DCACHE_NUM_REQ-1:0] thread_track_banks; // Valid thread mask per bank
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wire[`DCACHE_BANKS - 1 : 0][$clog2(`DCACHE_NUM_REQ)-1:0] index_per_bank; // Index of thread each bank will try to service
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wire[`DCACHE_BANKS - 1 : 0][`DCACHE_NUM_REQ-1:0] use_mask_per_bank; // A mask of index_per_bank
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wire[`DCACHE_BANKS - 1 : 0] valid_per_bank; // Valid request going to each bank
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wire[`DCACHE_BANKS - 1 : 0][`DCACHE_NUM_REQ-1:0] threads_serviced_per_bank; // Bank successfully serviced per bank
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wire[`DCACHE_BANKS-1:0][31:0] readdata_per_bank; // Data read from each bank
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wire[`DCACHE_BANKS-1:0] hit_per_bank; // Whether each bank got a hit or a miss
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wire[`DCACHE_BANKS-1:0] eviction_wb;
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reg[`DCACHE_BANKS-1:0] eviction_wb_old;
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wire[`DCACHE_BANKS -1 : 0][`DCACHE_WAY_INDEX-1:0] evicted_way_new;
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reg [`DCACHE_BANKS -1 : 0][`DCACHE_WAY_INDEX-1:0] evicted_way_old;
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wire[`DCACHE_BANKS -1 : 0][`DCACHE_WAY_INDEX-1:0] way_used;
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// Internal State
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reg [3:0] state;
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wire[3:0] new_state;
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wire[`DCACHE_NUM_REQ-1:0] use_valid; // Valid used throught the code
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reg[`DCACHE_NUM_REQ-1:0] stored_valid; // Saving the threads still left (bank conflict or bank miss)
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wire[`DCACHE_NUM_REQ-1:0] new_stored_valid; // New stored valid
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reg[`DCACHE_BANKS - 1 : 0][31:0] eviction_addr_per_bank;
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reg[31:0] miss_addr;
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reg[31:0] evict_addr;
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wire curr_processor_request_valid = (|i_p_valid);
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assign use_valid = (stored_valid == 0) ? i_p_valid : stored_valid;
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VX_cache_bank_valid #(.NUMBER_BANKS(`DCACHE_BANKS)) multip_banks(
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.i_p_valid (use_valid),
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.i_p_addr (i_p_addr),
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.thread_track_banks(thread_track_banks)
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);
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reg[`DCACHE_NUM_REQ-1:0] threads_serviced_Qual;
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reg[`DCACHE_NUM_REQ-1:0] debug_hit_per_bank_mask[`DCACHE_BANKS-1:0];
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genvar bid;
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for (bid = 0; bid < `DCACHE_BANKS; bid=bid+1)
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begin
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wire[`DCACHE_NUM_REQ-1:0] use_threads_track_banks = thread_track_banks[bid];
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wire[$clog2(`DCACHE_NUM_REQ)-1:0] use_thread_index = index_per_bank[bid];
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wire use_write_final_data = hit_per_bank[bid];
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wire[31:0] use_data_final_data = readdata_per_bank[bid];
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VX_priority_encoder_w_mask #(.N(`DCACHE_NUM_REQ)) choose_thread(
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.valids(use_threads_track_banks),
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.mask (use_mask_per_bank[bid]),
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.index (index_per_bank[bid]),
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.found (valid_per_bank[bid])
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);
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assign debug_hit_per_bank_mask[bid] = {`DCACHE_NUM_REQ{hit_per_bank[bid]}};
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assign threads_serviced_per_bank[bid] = use_mask_per_bank[bid] & debug_hit_per_bank_mask[bid];
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end
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integer test_bid;
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always @(*) begin
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new_final_data_read = 0;
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for (test_bid=0; test_bid < `DCACHE_BANKS; test_bid=test_bid+1)
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begin
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if (hit_per_bank[test_bid]) begin
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new_final_data_read[index_per_bank[test_bid]] = readdata_per_bank[test_bid];
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end
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end
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end
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wire[`DCACHE_BANKS - 1 : 0] detect_bank_miss;
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//assign threads_serviced_Qual = threads_serviced_per_bank[0] | threads_serviced_per_bank[1] |
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// threads_serviced_per_bank[2] | threads_serviced_per_bank[3] |
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// threads_serviced_per_bank[4] | threads_serviced_per_bank[5] |
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// threads_serviced_per_bank[6] | threads_serviced_per_bank[7];
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integer bbid;
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always @(*) begin
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threads_serviced_Qual = 0;
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for (bbid = 0; bbid < `DCACHE_BANKS; bbid=bbid+1)
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begin
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threads_serviced_Qual = threads_serviced_Qual | threads_serviced_per_bank[bbid];
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end
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end
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genvar tid;
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for (tid = 0; tid < `DCACHE_NUM_REQ; tid =tid+1)
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begin
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assign new_final_data_read_Qual[tid] = threads_serviced_Qual[tid] ? new_final_data_read[tid] : final_data_read[tid];
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end
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assign detect_bank_miss = (valid_per_bank & ~hit_per_bank);
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wire delay;
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assign delay = (new_stored_valid != 0) || (state != CACHE_IDLE); // add other states
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assign o_p_delay = delay;
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wire[`DCACHE_BANKS - 1 : 0][$clog2(`DCACHE_NUM_REQ)-1:0] send_index_to_bank = index_per_bank;
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wire[$clog2(`DCACHE_BANKS)-1:0] miss_bank_index;
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wire miss_found;
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VX_generic_priority_encoder #(.N(`DCACHE_BANKS)) get_miss_index
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.valids(detect_bank_miss),
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.index (miss_bank_index),
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.found (miss_found)
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);
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assign new_state = ((state == CACHE_IDLE) && (|detect_bank_miss)) ? SEND_MEM_REQ :
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(state == SEND_MEM_REQ) ? RECIV_MEM_RSP :
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((state == RECIV_MEM_RSP) && !i_m_ready) ? RECIV_MEM_RSP :
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CACHE_IDLE;
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// Handle if there is more than one miss
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assign new_stored_valid = use_valid & (~threads_serviced_Qual);
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///////////////////////////////////////////////////////////////////////
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genvar cur_t;
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integer init_b;
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always @(posedge clk, posedge rst) begin
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if (rst) begin
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final_data_read <= 0;
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// new_final_data_read = 0;
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state <= 0;
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stored_valid <= 0;
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// eviction_addr_per_bank <= 0;
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miss_addr <= 0;
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evict_addr <= 0;
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// threads_serviced_Qual = 0;
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// for (init_b = 0; init_b < NUMBER_BANKS; init_b=init_b+1)
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// begin
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// debug_hit_per_bank_mask[init_b] <= 0;
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// end
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evicted_way_old <= 0;
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eviction_wb_old <= 0;
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end else begin
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state <= new_state;
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stored_valid <= new_stored_valid;
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if (miss_found) begin
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miss_addr <= i_p_addr[send_index_to_bank[miss_bank_index]];
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evict_addr <= eviction_addr_per_bank[miss_bank_index];
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end
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final_data_read <= new_final_data_read_Qual;
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evicted_way_old <= evicted_way_new;
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eviction_wb_old <= eviction_wb;
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end
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end
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genvar bank_id;
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generate
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for (bank_id = 0; bank_id < `DCACHE_BANKS; bank_id = bank_id + 1)
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begin
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wire[31:0] bank_addr = (state == SEND_MEM_REQ) ? evict_addr :
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(state == RECIV_MEM_RSP) ? miss_addr :
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i_p_addr[send_index_to_bank[bank_id]];
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assign evicted_way_new[bank_id] = (state == SEND_MEM_REQ) ? way_used[bank_id] :
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(state == RECIV_MEM_RSP) ? evicted_way_old[bank_id] :
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0;
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wire[1:0] byte_select = bank_addr[1:0];
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wire[`DCACHE_OFFSET_SIZE_RNG] cache_offset = bank_addr[`DCACHE_ADDR_OFFSET_RNG];
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wire[`DCACHE_IND_SIZE_RNG] cache_index = bank_addr[`DCACHE_ADDR_IND_RNG];
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wire[`DCACHE_TAG_SIZE_RNG] cache_tag = bank_addr[`DCACHE_ADDR_TAG_RNG];
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wire normal_valid_in = valid_per_bank[bank_id];
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wire use_valid_in = ((state == RECIV_MEM_RSP) && i_m_ready) ? 1'b1 :
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((state == RECIV_MEM_RSP) && !i_m_ready) ? 1'b0 :
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((state == SEND_MEM_REQ)) ? 1'b0 :
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normal_valid_in;
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/*VX_Cache_Bank #(
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.CACHE_SIZE(CACHE_SIZE),
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.CACHE_WAYS(CACHE_WAYS),
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.CACHE_BLOCK(CACHE_BLOCK),
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.CACHE_BANKS(CACHE_BANKS)) bank_structure*/
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VX_Cache_Bank bank_structure(
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.clk (clk),
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.rst (rst),
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.state (state),
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.valid_in (use_valid_in),
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.actual_index (cache_index),
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.o_tag (cache_tag),
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.block_offset (cache_offset),
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.writedata (i_p_writedata[send_index_to_bank[bank_id]]),
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.read_or_write (i_p_read_or_write),
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.i_p_mem_read (i_p_mem_read),
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.i_p_mem_write (i_p_mem_write),
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.byte_select (byte_select),
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.hit (hit_per_bank[bank_id]),
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.readdata (readdata_per_bank[bank_id]), // Data read
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.eviction_addr (eviction_addr_per_bank[bank_id]),
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.data_evicted (o_m_writedata[bank_id]),
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.eviction_wb (eviction_wb[bank_id]), // Something needs to be written back
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.fetched_writedata(i_m_readdata[bank_id]), // Data From memory
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.evicted_way (evicted_way_new[bank_id]),
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.way_use (way_used[bank_id])
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);
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end
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endgenerate
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// Mem Rsp
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// Req to mem:
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assign o_m_evict_addr = evict_addr & 32'hffffffc0;
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assign o_m_read_addr = miss_addr & 32'hffffffc0;
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assign o_m_valid = (state == SEND_MEM_REQ);
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assign o_m_read_or_write = (state == SEND_MEM_REQ) && (|eviction_wb_old);
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//end
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endmodule
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