c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
78 lines
2.0 KiB
ArmAsm
78 lines
2.0 KiB
ArmAsm
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <VX_config.h>
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#include <VX_types.h>
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#define RISCV_CUSTOM0 0x0B
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.type vx_serial, @function
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.global vx_serial
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vx_serial:
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#if (XLEN == 64)
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addi sp, sp, -56
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sd ra, 48(sp)
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sd s5, 40(sp)
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sd s4, 32(sp)
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sd s3, 24(sp)
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sd s2, 16(sp)
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sd s1, 8(sp)
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sd s0, 0(sp)
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#else
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addi sp, sp, -28
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sw ra, 24(sp)
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sw s5, 20(sp)
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sw s4, 16(sp)
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sw s3, 12(sp)
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sw s2, 8(sp)
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sw s1, 4(sp)
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sw s0, 0(sp)
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#endif
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mv s4, a0 # s4 <- callback
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mv s3, a1 # s3 <- arg
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csrr s2, VX_CSR_NUM_THREADS # s2 <- NT
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csrr s1, VX_CSR_THREAD_ID # s1 <- tid
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li s0, 0 # s0 <- index
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label_loop:
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sub t0, s0, s1
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seqz t1, t0 # (index != tid)
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.insn r RISCV_CUSTOM0, 2, 0, s5, t1, x0 # split s5, t0
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bnez t0, label_join
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mv a0, s3 # a0 <- arg
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jalr s4 # callback(arg)
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label_join:
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.insn r RISCV_CUSTOM0, 3, 0, x0, s5, x0 # join s5
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addi s0, s0, 1 # index++
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blt s0, s2, label_loop # loop back
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#if (XLEN == 64)
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ld ra, 48(sp)
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ld s5, 40(sp)
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ld s4, 32(sp)
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ld s3, 24(sp)
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ld s2, 16(sp)
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ld s1, 8(sp)
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ld s0, 0(sp)
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addi sp, sp, 56
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#else
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lw ra, 24(sp)
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lw s5, 20(sp)
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lw s4, 16(sp)
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lw s3, 12(sp)
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lw s2, 8(sp)
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lw s1, 4(sp)
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lw s0, 0(sp)
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addi sp, sp, 28
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#endif
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ret
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