21 lines
684 B
Verilog
21 lines
684 B
Verilog
`include "VX_platform.vh"
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module VX_sat_fx #(
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parameter IN_W = 1,
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parameter OUT_W = 1,
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parameter MODEL = 1
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) (
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input wire [IN_W-1:0] data_in,
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output wire [OUT_W-1:0] data_out
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);
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`STATIC_ASSERT(((OUT_W+1) < IN_W), ("invalid parameter"))
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if (MODEL == 1) begin
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assign data_out = data_in[IN_W-1] ? OUT_W'(0) : ((data_in > {OUT_W{1'b1}}) ? {OUT_W{1'b1}} : OUT_W'(data_in));
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end else begin
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wire [OUT_W-1:0] underflow_mask = {OUT_W{~data_in[IN_W-1]}};
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wire [OUT_W-1:0] overflow_mask = {OUT_W{(| data_in[IN_W-2:OUT_W])}};
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assign data_out = (data_in[OUT_W-1:0] | overflow_mask) & underflow_mask;
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end
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endmodule |