17 lines
417 B
Verilog
17 lines
417 B
Verilog
`include "VX_tex_define.vh"
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module VX_tex_lerp #(
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) (
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input wire [`BLEND_FRAC-1:0] blend,
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input wire [31:0] in1,
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input wire [31:0] in2,
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output wire [31:0] out
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);
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for (genvar i = 0; i < 4; ++i) begin
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wire [8:0] m1 = (8'hff - blend);
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wire [16:0] sum = in1[i*8+:8] * blend + in2[i*8+:8] * m1;
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`UNUSED_VAR (sum)
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assign out[i*8+:8] = sum[15:8];
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end
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endmodule |