19 lines
435 B
Verilog
19 lines
435 B
Verilog
`include "VX_platform.vh"
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module VX_mux #(
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parameter DATAW = 1,
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parameter N = 1,
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parameter LN = $clog2(N)
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) (
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input wire [N-1:0][DATAW-1:0] data_in,
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input wire [LN-1:0] sel_in,
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output wire [DATAW-1:0] data_out
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);
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if (N > 1) begin
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assign data_out = data_in[sel_in];
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end else begin
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`UNUSED_VAR (sel_in)
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assign data_out = data_in;
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end
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endmodule |