25 lines
654 B
Verilog
25 lines
654 B
Verilog
`ifndef VX_GPU_DCACHE_RSP
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`define VX_GPU_DCACHE_RSP
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`include "../cache/VX_cache_config.vh"
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interface VX_gpu_dcache_rsp_if #(
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parameter NUM_REQUESTS = 32
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) ();
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// Core response
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wire [NUM_REQUESTS-1:0] core_rsp_valid;
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`IGNORE_WARNINGS_BEGIN
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wire [4:0] core_rsp_read;
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wire [1:0] core_rsp_write;
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`IGNORE_WARNINGS_END
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wire [NUM_REQUESTS-1:0][31:0] core_rsp_pc;
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wire [NUM_REQUESTS-1:0][31:0] core_rsp_data;
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wire core_rsp_ready;
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// Core response meta data
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wire [`NW_BITS-1:0] core_rsp_warp_num;
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endinterface
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`endif |