Files
kernels/hw/rtl/interfaces/VX_csr_wb_if.v
2020-04-20 12:51:42 -07:00

17 lines
305 B
Verilog

`ifndef VX_CSR_WB_REQ
`define VX_CSR_WB_REQ
`include "../VX_define.vh"
interface VX_csr_wb_if ();
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire [4:0] rd;
wire [1:0] wb;
wire [`NUM_THREADS-1:0][31:0] csr_result;
endinterface
`endif