267 lines
12 KiB
Verilog
267 lines
12 KiB
Verilog
`include "VX_define.vh"
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`include "VX_cache_config.vh"
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module Vortex_Socket (
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// Clock
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input wire clk,
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input wire reset,
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// IO
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output wire io_valid[(`NUM_CORES * `NUM_CLUSTERS)-1:0],
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output wire[31:0] io_data [(`NUM_CORES * `NUM_CLUSTERS)-1:0],
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// DRAM Req
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output wire dram_req_read,
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output wire dram_req_write,
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output wire [31:0] dram_req_addr,
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output wire [`DBANK_LINE_SIZE-1:0] dram_req_data,
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input wire dram_req_ready,
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// DRAM Rsp
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input wire dram_rsp_valid,
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input wire [31:0] dram_rsp_addr,
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input wire [`DBANK_LINE_SIZE-1:0] dram_rsp_data,
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output wire dram_rsp_ready,
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// LLC Snooping
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input wire llc_snp_req_valid,
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input wire[31:0] llc_snp_req_addr,
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output wire llc_snp_req_ready,
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output wire ebreak
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);
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if (`NUM_CLUSTERS == 1) begin
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wire[`NUM_CORES-1:0] cluster_io_valid;
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wire[`NUM_CORES-1:0][31:0] cluster_io_data;
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genvar curr_c;
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for (curr_c = 0; curr_c < `NUM_CORES; curr_c=curr_c+1) begin
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assign io_valid[curr_c] = cluster_io_valid[curr_c];
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assign io_data [curr_c] = cluster_io_data [curr_c];
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end
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Vortex_Cluster #(
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.CLUSTER_ID(0)
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) Vortex_Cluster (
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.clk (clk),
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.reset (reset),
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.io_valid (cluster_io_valid),
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.io_data (cluster_io_data),
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.dram_req_read (dram_req_read),
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.dram_req_write (dram_req_write),
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.dram_req_addr (dram_req_addr),
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.dram_req_data (dram_req_data),
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.dram_req_ready (dram_req_ready),
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.dram_rsp_valid (dram_rsp_valid),
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.dram_rsp_addr (dram_rsp_addr),
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.dram_rsp_data (dram_rsp_data),
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.dram_rsp_ready (dram_rsp_ready),
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.llc_snp_req_valid (llc_snp_req_valid),
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.llc_snp_req_addr (llc_snp_req_addr),
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.llc_snp_req_ready (llc_snp_req_ready),
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.ebreak (ebreak)
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);
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end else begin
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wire snp_fwd_valid;
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wire[31:0] snp_fwd_addr;
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wire[`NUM_CLUSTERS-1:0] snp_fwd_ready;
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wire[`NUM_CLUSTERS-1:0] per_cluster_ebreak;
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assign ebreak = (&per_cluster_ebreak);
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// // DRAM Dcache Req
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wire[`NUM_CLUSTERS-1:0] per_cluster_dram_req_valid;
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wire[`NUM_CLUSTERS-1:0] per_cluster_dram_req_write;
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wire[`NUM_CLUSTERS-1:0] per_cluster_dram_req_read;
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wire[`NUM_CLUSTERS-1:0] [31:0] per_cluster_dram_req_addr;
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wire[`NUM_CLUSTERS-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_cluster_dram_req_data;
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wire[31:0] per_cluster_dram_req_data_up[`NUM_CLUSTERS-1:0][`DBANK_LINE_WORDS-1:0];
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wire l3c_core_req_ready;
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// // DRAM Dcache Rsp
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wire[`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_ready;
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wire[`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_valid;
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wire[`NUM_CLUSTERS-1:0] [31:0] per_cluster_dram_rsp_addr;
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wire[`NUM_CLUSTERS-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_cluster_dram_rsp_data;
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wire[31:0] per_cluster_dram_rsp_data_up[`NUM_CLUSTERS-1:0][`DBANK_LINE_WORDS-1:0];
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wire[`NUM_CLUSTERS-1:0][`NUM_CORES-1:0] per_cluster_io_valid;
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wire[`NUM_CLUSTERS-1:0][`NUM_CORES-1:0][31:0] per_cluster_io_data;
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genvar curr_c, curr_cc, curr_word;
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for (curr_c = 0; curr_c < `NUM_CLUSTERS; curr_c =curr_c+1) begin
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for (curr_cc = 0; curr_cc < `NUM_CORES; curr_cc=curr_cc+1) begin
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assign io_valid[curr_cc+(curr_c*`NUM_CORES)] = per_cluster_io_valid[curr_c][curr_cc];
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assign io_data [curr_cc+(curr_c*`NUM_CORES)] = per_cluster_io_data [curr_c][curr_cc];
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end
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for (curr_word = 0; curr_word < `DBANK_LINE_WORDS; curr_word = curr_word+1) begin
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assign per_cluster_dram_req_data [curr_c][curr_word] = per_cluster_dram_req_data_up [curr_c][curr_word];
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assign per_cluster_dram_rsp_data_up[curr_c][curr_word] = per_cluster_dram_rsp_data[curr_c][curr_word];
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end
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end
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genvar curr_cluster;
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for (curr_cluster = 0; curr_cluster < `NUM_CLUSTERS; curr_cluster=curr_cluster+1) begin
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Vortex_Cluster #(
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.CLUSTER_ID(curr_cluster)
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) Vortex_Cluster (
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.clk (clk),
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.reset (reset),
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.io_valid (per_cluster_io_valid [curr_cluster]),
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.io_data (per_cluster_io_data [curr_cluster]),
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.dram_req_write (per_cluster_dram_req_write [curr_cluster]),
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.dram_req_read (per_cluster_dram_req_read [curr_cluster]),
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.dram_req_addr (per_cluster_dram_req_addr [curr_cluster]),
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.dram_req_data (per_cluster_dram_req_data_up [curr_cluster]),
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.dram_req_ready (l3c_core_req_ready),
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.dram_rsp_valid (per_cluster_dram_rsp_valid [curr_cluster]),
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.dram_rsp_addr (per_cluster_dram_rsp_addr [curr_cluster]),
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.dram_rsp_data (per_cluster_dram_rsp_data_up [curr_cluster]),
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.dram_rsp_ready (per_cluster_dram_rsp_ready [curr_cluster]),
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.llc_snp_req_valid (snp_fwd_valid),
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.llc_snp_req_addr (snp_fwd_addr),
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.llc_snp_req_ready (snp_fwd_ready [curr_cluster]),
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.ebreak (per_cluster_ebreak [curr_cluster])
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);
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end
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//////////////////// L3 Cache ////////////////////
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wire[`L3NUM_REQUESTS-1:0] l3c_core_req_valid;
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wire[`L3NUM_REQUESTS-1:0][2:0] l3c_core_req_mem_write;
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wire[`L3NUM_REQUESTS-1:0][2:0] l3c_core_req_mem_read;
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wire[`L3NUM_REQUESTS-1:0][31:0] l3c_core_req_addr;
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wire[`L3NUM_REQUESTS-1:0][`IBANK_LINE_WORDS-1:0][31:0] l3c_core_req_data;
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wire[`L3NUM_REQUESTS-1:0][1:0] l3c_core_req_wb;
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wire[`L3NUM_REQUESTS-1:0] l3c_core_rsp_ready;
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wire[`L3NUM_REQUESTS-1:0] l3c_wb;
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wire[`L3NUM_REQUESTS-1:0] [31:0] l3c_wb_addr;
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wire[`L3NUM_REQUESTS-1:0][`IBANK_LINE_WORDS-1:0][31:0] l3c_wb_data;
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wire[`DBANK_LINE_WORDS-1:0][31:0] dram_req_data_port;
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wire[`DBANK_LINE_WORDS-1:0][31:0] dram_rsp_data_port;
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genvar llb_index;
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for (llb_index = 0; llb_index < `DBANK_LINE_WORDS; llb_index=llb_index+1) begin
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assign dram_req_data [llb_index] = dram_req_data_port[llb_index];
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assign dram_rsp_data_port[llb_index] = dram_rsp_data[llb_index];
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end
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genvar l3c_curr_cluster;
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for (l3c_curr_cluster = 0; l3c_curr_cluster < `L3NUM_REQUESTS; l3c_curr_cluster=l3c_curr_cluster+1) begin
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// Core Request
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assign l3c_core_req_valid [l3c_curr_cluster] = per_cluster_dram_req_valid[l3c_curr_cluster];
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assign l3c_core_req_mem_read [l3c_curr_cluster] = per_cluster_dram_req_read [l3c_curr_cluster] ? `LW_MEM_READ : `NO_MEM_READ;
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assign l3c_core_req_mem_write [l3c_curr_cluster] = per_cluster_dram_req_write[l3c_curr_cluster] ? `SW_MEM_WRITE : `NO_MEM_WRITE;
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assign l3c_core_req_wb [l3c_curr_cluster] = per_cluster_dram_req_read [l3c_curr_cluster] ? 1 : 0;
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assign l3c_core_req_addr [l3c_curr_cluster] = per_cluster_dram_req_addr [l3c_curr_cluster];
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assign l3c_core_req_data [l3c_curr_cluster] = per_cluster_dram_req_data [l3c_curr_cluster];
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// Core can't accept Response
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assign l3c_core_rsp_ready [l3c_curr_cluster] = per_cluster_dram_rsp_ready[l3c_curr_cluster];
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// Cache Fill Response
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assign per_cluster_dram_rsp_valid [l3c_curr_cluster] = l3c_wb [l3c_curr_cluster];
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assign per_cluster_dram_rsp_data [l3c_curr_cluster] = l3c_wb_data [l3c_curr_cluster];
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assign per_cluster_dram_rsp_addr [l3c_curr_cluster] = l3c_wb_addr [l3c_curr_cluster];
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end
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VX_cache #(
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.CACHE_SIZE_BYTES (`L3CACHE_SIZE_BYTES),
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.BANK_LINE_SIZE_BYTES (`L3BANK_LINE_SIZE_BYTES),
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.NUM_BANKS (`L3NUM_BANKS),
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.WORD_SIZE_BYTES (`L3WORD_SIZE_BYTES),
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.NUM_REQUESTS (`L3NUM_REQUESTS),
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.STAGE_1_CYCLES (`L3STAGE_1_CYCLES),
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.FUNC_ID (`L2FUNC_ID),
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.REQQ_SIZE (`L3REQQ_SIZE),
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.MRVQ_SIZE (`L3MRVQ_SIZE),
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.DFPQ_SIZE (`L3DFPQ_SIZE),
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.SNRQ_SIZE (`L3SNRQ_SIZE),
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.CWBQ_SIZE (`L3CWBQ_SIZE),
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.DWBQ_SIZE (`L3DWBQ_SIZE),
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.DFQQ_SIZE (`L3DFQQ_SIZE),
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.LLVQ_SIZE (`L3LLVQ_SIZE),
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.FFSQ_SIZE (`L3FFSQ_SIZE),
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.PRFQ_SIZE (`L3PRFQ_SIZE),
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.PRFQ_STRIDE (`L3PRFQ_STRIDE),
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.FILL_INVALIDAOR_SIZE (`L3FILL_INVALIDAOR_SIZE),
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.SIMULATED_DRAM_LATENCY_CYCLES(`L3SIMULATED_DRAM_LATENCY_CYCLES)
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) gpu_l3cache (
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.clk (clk),
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.reset (reset),
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// Core Req (DRAM Fills/WB) To L2 Request
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.core_req_valid (l3c_core_req_valid),
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.core_req_read (l3c_core_req_mem_read),
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.core_req_write (l3c_core_req_mem_write),
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.core_req_addr (l3c_core_req_addr),
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.core_req_data ({l3c_core_req_data}),
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.core_req_rd (0),
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.core_req_wb (l3c_core_req_wb),
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.core_req_warp_num (0),
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.core_req_pc (0),
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// L2 can't accept Core Request
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.core_req_ready (l3c_core_req_ready),
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// Core can't accept L2 Request
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.core_rsp_ready (|l3c_core_rsp_ready),
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// Core Writeback
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.core_rsp_valid (l3c_wb),
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`IGNORE_WARNINGS_BEGIN
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.core_rsp_read (),
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.core_rsp_write (),
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.core_rsp_warp_num (),
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.core_rsp_pc (),
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`IGNORE_WARNINGS_END
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.core_rsp_data ({l3c_wb_data}),
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.core_rsp_addr (l3c_wb_addr),
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// L2 Cache DRAM Fill response
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.dram_rsp_valid (dram_rsp_valid),
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.dram_rsp_addr (dram_rsp_addr),
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.dram_rsp_data ({dram_rsp_data_port}),
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// L2 Cache can't accept Fill Response
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.dram_rsp_ready (dram_rsp_ready),
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// L2 Cache DRAM Fill Request
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.dram_req_write (dram_req_write),
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.dram_req_read (dram_req_read),
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.dram_req_addr (dram_req_addr),
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.dram_req_data ({dram_req_data_port}),
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.dram_req_ready (dram_req_ready),
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// Snoop Request
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.snp_req_valid (llc_snp_req_valid),
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.snp_req_addr (llc_snp_req_addr),
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.snp_req_ready (llc_snp_req_ready),
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// Snoop Forward
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.snp_fwd_valid (snp_fwd_valid),
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.snp_fwd_addr (snp_fwd_addr),
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.snp_fwd_ready (& snp_fwd_ready)
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);
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end
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endmodule |