90 lines
2.9 KiB
Verilog
90 lines
2.9 KiB
Verilog
`include "VX_platform.vh"
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// Fast encoder using parallel prefix computation
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// Adapter from BaseJump STL: http://bjump.org/data_out.html
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module VX_onehot_encoder #(
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parameter N = 1,
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parameter LN = `LOG2UP(N)
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) (
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input wire [N-1:0] data_in,
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output wire [LN-1:0] data_out,
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output wire valid
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);
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if (N == 1) begin
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assign data_out = data_in;
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assign valid = data_in;
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end else if (N == 2) begin
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assign data_out = data_in[1];
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assign valid = (| data_in);
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end else begin
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reg [LN-1:0] index_r;
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if (N == 4) begin
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always @(*) begin
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casez (data_in)
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4'b0001: index_r = LN'(0);
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4'b001?: index_r = LN'(1);
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4'b01??: index_r = LN'(2);
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4'b1???: index_r = LN'(3);
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default: index_r = 'x;
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endcase
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end
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end else if (N == 8) begin
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always @(*) begin
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casez (data_in)
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8'b00000001: index_r = LN'(0);
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8'b0000001?: index_r = LN'(1);
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8'b000001??: index_r = LN'(2);
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8'b00001???: index_r = LN'(3);
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8'b0001????: index_r = LN'(4);
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8'b001?????: index_r = LN'(5);
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8'b01??????: index_r = LN'(6);
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8'b1???????: index_r = LN'(7);
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default: index_r = 'x;
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endcase
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end
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end else if (N == 16) begin
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always @(*) begin
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casez (data_in)
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16'b0000000000000001: index_r = LN'(0);
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16'b000000000000001?: index_r = LN'(1);
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16'b00000000000001??: index_r = LN'(2);
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16'b0000000000001???: index_r = LN'(3);
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16'b000000000001????: index_r = LN'(4);
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16'b00000000001?????: index_r = LN'(5);
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16'b0000000001??????: index_r = LN'(6);
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16'b000000001???????: index_r = LN'(7);
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16'b00000001????????: index_r = LN'(8);
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16'b0000001?????????: index_r = LN'(9);
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16'b000001??????????: index_r = LN'(10);
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16'b00001???????????: index_r = LN'(11);
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16'b0001????????????: index_r = LN'(12);
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16'b001?????????????: index_r = LN'(13);
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16'b01??????????????: index_r = LN'(14);
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16'b1???????????????: index_r = LN'(15);
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default: index_r = 'x;
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endcase
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end
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end else begin
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always @(*) begin
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index_r = 'x;
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for (integer i = 0; i < N; i++) begin
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if (data_in[i]) begin
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index_r = `LOG2UP(N)'(i);
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end
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end
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end
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end
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assign data_out = index_r;
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assign valid = (| data_in);
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end
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endmodule |