19 lines
271 B
Verilog
19 lines
271 B
Verilog
`ifndef VX_CMT_TO_CSR_IF
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`define VX_CMT_TO_CSR_IF
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`include "VX_define.vh"
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interface VX_cmt_to_csr_if ();
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wire valid;
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wire [`NW_BITS-1:0] warp_num;
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wire [`NE_BITS:0] num_commits;
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wire has_fflags;
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wire [`FFG_BITS-1:0] fflags;
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endinterface
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`endif |