167 lines
6.4 KiB
Verilog
167 lines
6.4 KiB
Verilog
`include "VX_platform.vh"
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`include "VX_define.vh"
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module VX_tex_unit #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// Inputs
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VX_tex_req_if tex_req_if,
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VX_tex_csr_if tex_csr_if,
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// Outputs
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VX_tex_rsp_if tex_rsp_if,
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// Texture unit <-> Memory Unit
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VX_dcache_core_req_if dcache_req_if,
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VX_dcache_core_rsp_if dcache_rsp_if
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);
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`UNUSED_PARAM (CORE_ID)
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`UNUSED_VAR (reset)
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wire rsp_valid;
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wire [`NW_BITS-1:0] rsp_wid;
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wire [`NUM_THREADS-1:0] rsp_tmask;
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wire [31:0] rsp_PC;
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wire [`NR_BITS-1:0] rsp_rd;
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wire rsp_wb;
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wire [`NUM_THREADS-1:0][31:0] rsp_data;
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wire stall_in, stall_out;
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reg [`CSR_WIDTH-1:0] tex_addr [`NUM_TEX_UNITS-1: 0];
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reg [`CSR_WIDTH-1:0] tex_format [`NUM_TEX_UNITS-1: 0];
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reg [`CSR_WIDTH-1:0] tex_width [`NUM_TEX_UNITS-1: 0];
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reg [`CSR_WIDTH-1:0] tex_height [`NUM_TEX_UNITS-1: 0];
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reg [`CSR_WIDTH-1:0] tex_stride [`NUM_TEX_UNITS-1: 0];
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reg [`CSR_WIDTH-1:0] tex_wrap_u [`NUM_TEX_UNITS-1: 0];
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reg [`CSR_WIDTH-1:0] tex_wrap_v [`NUM_TEX_UNITS-1: 0];
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reg [`CSR_WIDTH-1:0] tex_min_filter [`NUM_TEX_UNITS-1: 0];
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reg [`CSR_WIDTH-1:0] tex_max_filter [`NUM_TEX_UNITS-1: 0];
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`UNUSED_VAR (tex_addr)
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`UNUSED_VAR (tex_format)
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`UNUSED_VAR (tex_width)
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`UNUSED_VAR (tex_height)
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`UNUSED_VAR (tex_stride)
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`UNUSED_VAR (tex_wrap_u)
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`UNUSED_VAR (tex_wrap_v)
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`UNUSED_VAR (tex_min_filter)
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`UNUSED_VAR (tex_max_filter)
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//tex csr programming, need to make make consistent with `NUM_TEX_UNITS
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always @(posedge clk ) begin
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if (tex_csr_if.write_enable) begin
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case (tex_csr_if.write_addr)
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`CSR_TEX0_ADDR : tex_addr[0] <= tex_csr_if.write_data;
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`CSR_TEX0_FORMAT : tex_format[0] <= tex_csr_if.write_data;
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`CSR_TEX0_WIDTH : tex_width[0] <= tex_csr_if.write_data;
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`CSR_TEX0_HEIGHT : tex_height[0] <= tex_csr_if.write_data;
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`CSR_TEX0_PITCH : tex_stride[0] <= tex_csr_if.write_data;
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`CSR_TEX0_WRAP_U : tex_wrap_u[0] <= tex_csr_if.write_data;
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`CSR_TEX0_WRAP_V : tex_wrap_v[0] <= tex_csr_if.write_data;
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`CSR_TEX0_MIN_FILTER : tex_min_filter[0] <= tex_csr_if.write_data;
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`CSR_TEX0_MAX_FILTER : tex_max_filter[0] <= tex_csr_if.write_data;
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`CSR_TEX1_ADDR : tex_addr[1] <= tex_csr_if.write_data;
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`CSR_TEX1_FORMAT : tex_format[1] <= tex_csr_if.write_data;
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`CSR_TEX1_WIDTH : tex_width[1] <= tex_csr_if.write_data;
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`CSR_TEX1_HEIGHT : tex_height[1] <= tex_csr_if.write_data;
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`CSR_TEX1_PITCH : tex_stride[1] <= tex_csr_if.write_data;
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`CSR_TEX1_WRAP_U : tex_wrap_u[1] <= tex_csr_if.write_data;
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`CSR_TEX1_WRAP_V : tex_wrap_v[1] <= tex_csr_if.write_data;
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`CSR_TEX1_MIN_FILTER : tex_min_filter[1] <= tex_csr_if.write_data;
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`CSR_TEX1_MAX_FILTER : tex_max_filter[1] <= tex_csr_if.write_data;
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default:;
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endcase
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end
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end
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// texture response
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`UNUSED_VAR (tex_req_if.u)
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`UNUSED_VAR (tex_req_if.v)
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`UNUSED_VAR (tex_req_if.lod)
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`UNUSED_VAR (tex_req_if.t)
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assign stall_in = stall_out;
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assign rsp_valid = tex_req_if.valid;
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assign rsp_wid = tex_req_if.wid;
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assign rsp_tmask = tex_req_if.tmask;
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assign rsp_PC = tex_req_if.PC;
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assign rsp_rd = tex_req_if.rd;
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assign rsp_wb = tex_req_if.wb;
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assign rsp_data = {`NUM_THREADS{32'hFF0000FF}}; // dummy blue value
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/*//point sampling texel address computation
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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assign tex_req_if.u[i] = gpu_req_if.rs1_data[i];
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assign tex_req_if.v[i] = gpu_req_if.rs2_data[i];
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assign tex_req_if.lod[i] = gpu_req_if.rs3_data[i][31:8];
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assign tex_req_if.t[i] = gpu_req_if.rs3_data[i][7:0];
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VX_tex_pt_addr #(
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) tex_pt_addr (
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.clk (clk),
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.reset (reset),
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);
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end*/
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// fifo/wait buffer for fragments and also to dcache
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// texture unit <-> dcache
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VX_lsu_req_if lsu_req_if();
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VX_commit_if ld_commit_if();
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VX_tex_memory #(
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.CORE_ID(CORE_ID)
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) tex_memory (
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.clk (clk),
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.reset (reset),
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.dcache_req_if (dcache_req_if),
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.dcache_rsp_if (dcache_rsp_if),
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.lsu_req_if (lsu_req_if),
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.ld_commit_if (ld_commit_if)
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);
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// output
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assign stall_out = ~tex_rsp_if.ready && tex_rsp_if.valid;
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VX_pipe_register #(
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.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32)),
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.RESETW (1)
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) pipe_reg (
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.clk (clk),
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.reset (reset),
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.enable (~stall_out),
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.data_in ({rsp_valid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, rsp_data}),
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.data_out ({tex_rsp_if.valid, tex_rsp_if.wid, tex_rsp_if.tmask, tex_rsp_if.PC, tex_rsp_if.rd, tex_rsp_if.wb, tex_rsp_if.data})
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);
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// can accept new request?
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assign tex_req_if.ready = ~stall_in;
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`ifdef DBG_PRINT_TEX
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always @(posedge clk) begin
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if (tex_csr_if.write_enable
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&& (tex_csr_if.write_addr <= `CSR_TEX_END
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|| tex_csr_if.write_addr >= `CSR_TEX_BEGIN)) begin
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$display("%t: core%0d-tex_csr: csr_tex0_addr, csr_data=%0h", $time, CORE_ID, tex_addr[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_format, csr_data=%0h", $time, CORE_ID, tex_format[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_width, csr_data=%0h", $time, CORE_ID, tex_width[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_height, csr_data=%0h", $time, CORE_ID, tex_height[0]);
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$display("%t: core%0d-tex_csr: CSR_TEX0_PITCH, csr_data=%0h", $time, CORE_ID, tex_stride[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_wrap_u, csr_data=%0h", $time, CORE_ID, tex_wrap_u[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_wrap_v, csr_data=%0h", $time, CORE_ID, tex_wrap_v[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_min_filter, csr_data=%0h", $time, CORE_ID, tex_min_filter[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_max_filter, csr_data=%0h", $time, CORE_ID, tex_max_filter[0]);
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end
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end
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`endif
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endmodule |