felsabbagh3 b7af8c3f34 Integrated Shared Memory

2019-10-22 05:03:47 -04:00

..

191017.log

added log file

2019-10-17 14:00:22 -04:00

dc_noOpt.log

Finished synthesis with no optimization, cell count increasts to 100k

2019-10-21 17:53:51 -04:00

dc.log

Added log file of synthesis, too many registers are removed

2019-10-17 14:25:54 -04:00

syn.tcl

Integrated Shared Memory

2019-10-22 05:03:47 -04:00