230 lines
8.3 KiB
Verilog
230 lines
8.3 KiB
Verilog
`include "VX_define.vh"
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module VX_ibuffer #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// inputs
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input wire freeze, // keep current warp
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VX_decode_if ibuf_enq_if,
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// outputs
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VX_decode_if ibuf_deq_if
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);
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localparam DATAW = `NUM_THREADS + 32 + `EX_BITS + `OP_BITS + `FRM_BITS + 1 + (`NR_BITS * 4) + 32 + 1 + 1 + `NUM_REGS;
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localparam SIZE = `IBUF_SIZE;
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localparam ADDRW = $clog2(SIZE);
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localparam NWARPSW = $clog2(`NUM_WARPS+1);
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reg [`NUM_WARPS-1:0][ADDRW-1:0] used_r;
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reg [`NUM_WARPS-1:0] full_r, empty_r, sizeMany_r;
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wire [`NUM_WARPS-1:0] q_full, q_empty;
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wire [`NUM_WARPS-1:0] q_sizeMany;
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wire [DATAW-1:0] q_data_in;
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wire [`NUM_WARPS-1:0][DATAW-1:0] q_data_prev;
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reg [`NUM_WARPS-1:0][DATAW-1:0] q_data_out;
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wire enq_fire = ibuf_enq_if.valid && ibuf_enq_if.ready;
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wire deq_fire = ibuf_deq_if.valid && ibuf_deq_if.ready;
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for (genvar i = 0; i < `NUM_WARPS; ++i) begin
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wire writing = enq_fire && (i == ibuf_enq_if.wid);
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wire reading = deq_fire && (i == ibuf_deq_if.wid);
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wire is_slot0 = (0 == used_r[i]) || ((1 == used_r[i]) && reading);
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wire push = writing && !is_slot0;
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wire pop = reading && sizeMany_r[i];
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VX_generic_queue #(
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.DATAW (DATAW),
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.SIZE (SIZE),
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.BUFFERED (1),
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.FASTRAM (1)
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) queue (
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.clk (clk),
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.reset (reset),
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.push (push),
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.pop (pop),
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.data_in (q_data_in),
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.data_out (q_data_prev[i]),
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`UNUSED_PIN (empty),
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`UNUSED_PIN (full),
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`UNUSED_PIN (size)
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);
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always @(posedge clk) begin
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if (reset) begin
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used_r[i] <= 0;
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full_r[i] <= 0;
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empty_r[i] <= 1;
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sizeMany_r[i] <= 0;
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end else begin
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if (writing && !reading) begin
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empty_r[i] <= 0;
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if (used_r[i] == ADDRW'(SIZE-1)) begin
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full_r[i] <= 1;
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end
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if (used_r[i] == 1) begin
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sizeMany_r[i] <= 1;
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end
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end
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if (reading && !writing) begin
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full_r[i] <= 0;
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if (used_r[i] == ADDRW'(1)) begin
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empty_r[i] <= 1;
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end
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if (used_r[i] == ADDRW'(2)) begin
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sizeMany_r[i] <= 0;
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end
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end
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used_r[i] <= used_r[i] + ADDRW'($signed(2'(writing) - 2'(reading)));
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end
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if (writing && is_slot0) begin
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q_data_out[i] <= q_data_in;
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end
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if (pop) begin
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q_data_out[i] <= q_data_prev[i];
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end
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end
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assign q_full[i] = full_r[i];
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assign q_empty[i] = empty_r[i];
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assign q_sizeMany[i] = sizeMany_r[i];
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end
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///////////////////////////////////////////////////////////////////////////
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reg [`NUM_WARPS-1:0] valid_table, valid_table_n;
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reg [`NUM_WARPS-1:0] schedule_table, schedule_table_n;
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reg [NWARPSW-1:0] num_warps;
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reg [`NW_BITS-1:0] deq_wid, deq_wid_n;
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reg deq_valid, deq_valid_n;
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reg [DATAW-1:0] deq_instr, deq_instr_n;
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always @(*) begin
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valid_table_n = valid_table;
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if (deq_fire) begin
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valid_table_n[deq_wid] = q_sizeMany[deq_wid];
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end
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if (enq_fire) begin
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valid_table_n[ibuf_enq_if.wid] = 1;
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end
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end
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// schedule the next instruction to issue
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// do round-robin when multiple warps are active
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always @(*) begin
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deq_valid_n = 0;
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deq_wid_n = 'x;
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deq_instr_n = 'x;
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schedule_table_n = schedule_table;
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if (0 == num_warps) begin
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deq_valid_n = enq_fire;
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deq_wid_n = ibuf_enq_if.wid;
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deq_instr_n = q_data_in;
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end else if ((1 == num_warps) || freeze) begin
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deq_valid_n = (!deq_fire || q_sizeMany[deq_wid]) || enq_fire;
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deq_wid_n = (!deq_fire || q_sizeMany[deq_wid]) ? deq_wid : ibuf_enq_if.wid;
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deq_instr_n = deq_fire ? (q_sizeMany[deq_wid] ? q_data_prev[deq_wid] : q_data_in) : q_data_out[deq_wid];
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end else begin
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deq_valid_n = (| schedule_table_n);
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for (integer i = 0; i < `NUM_WARPS; i++) begin
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if (schedule_table_n[i]) begin
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deq_wid_n = `NW_BITS'(i);
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deq_instr_n = q_data_out[i];
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schedule_table_n[i] = 0;
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break;
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end
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end
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end
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end
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wire warp_added = enq_fire && q_empty[ibuf_enq_if.wid];
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wire warp_removed = deq_fire && ~(enq_fire && ibuf_enq_if.wid == deq_wid) && ~q_sizeMany[deq_wid];
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always @(posedge clk) begin
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if (reset) begin
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valid_table <= 0;
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schedule_table <= 0;
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deq_valid <= 0;
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num_warps <= 0;
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end else begin
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valid_table <= valid_table_n;
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if ((| schedule_table_n)) begin
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schedule_table <= schedule_table_n;
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end else begin
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schedule_table <= valid_table_n;
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schedule_table[deq_wid_n] <= 0;
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end
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deq_valid <= deq_valid_n;
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deq_wid <= deq_wid_n;
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deq_instr <= deq_instr_n;
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if (warp_added && !warp_removed) begin
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num_warps <= num_warps + NWARPSW'(1);
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end else if (warp_removed && !warp_added) begin
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num_warps <= num_warps - NWARPSW'(1);
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end
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`ifdef VERILATOR
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/*if (enq_fire || deq_fire || deq_valid) begin
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$display("*** %t: cur=%b(%0d), nxt=%b(%0d), enq=%b(%0d), deq=%b(%0d), nw=%0d(%0d,%0d,%0d,%0d), sched=%b, sched_n=%b",
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$time, deq_valid, deq_wid, deq_valid_n, deq_wid_n, enq_fire, ibuf_enq_if.wid, deq_fire, ibuf_deq_if.wid, num_warps, used_r[0], used_r[1], used_r[2], used_r[3], schedule_table, schedule_table_n);
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end*/
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begin // verify 'num_warps'
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integer nw = 0;
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for (integer i = 0; i < `NUM_WARPS; i++) begin
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nw += 32'(!q_empty[i]);
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end
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assert(nw == 32'(num_warps)) else $error("%t: error: invalid num_warps: nw=%0d, ref=%0d", $time, num_warps, nw);
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assert(~deq_valid || !q_empty[deq_wid]) else $error("%t: error: invalid schedule: wid=%0d", $time, deq_wid);
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assert(~deq_fire || !q_empty[deq_wid]) else $error("%t: error: invalid dequeu: wid=%0d", $time, deq_wid);
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end
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`endif
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end
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end
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assign ibuf_enq_if.ready = ~q_full[ibuf_enq_if.wid];
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assign q_data_in = {ibuf_enq_if.tmask,
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ibuf_enq_if.PC,
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ibuf_enq_if.ex_type,
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ibuf_enq_if.op_type,
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ibuf_enq_if.op_mod,
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ibuf_enq_if.wb,
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ibuf_enq_if.rd,
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ibuf_enq_if.rs1,
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ibuf_enq_if.rs2,
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ibuf_enq_if.rs3,
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ibuf_enq_if.imm,
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ibuf_enq_if.rs1_is_PC,
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ibuf_enq_if.rs2_is_imm,
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ibuf_enq_if.used_regs};
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assign ibuf_deq_if.valid = deq_valid;
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assign ibuf_deq_if.wid = deq_wid;
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assign {ibuf_deq_if.tmask,
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ibuf_deq_if.PC,
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ibuf_deq_if.ex_type,
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ibuf_deq_if.op_type,
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ibuf_deq_if.op_mod,
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ibuf_deq_if.wb,
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ibuf_deq_if.rd,
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ibuf_deq_if.rs1,
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ibuf_deq_if.rs2,
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ibuf_deq_if.rs3,
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ibuf_deq_if.imm,
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ibuf_deq_if.rs1_is_PC,
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ibuf_deq_if.rs2_is_imm,
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ibuf_deq_if.used_regs} = deq_instr;
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endmodule |