88 lines
1.7 KiB
Verilog
88 lines
1.7 KiB
Verilog
`include "VX_cache_config.v"
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module VX_fill_invalidator (
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input wire clk,
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input wire reset,
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input wire possible_fill,
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input wire success_fill,
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input wire[31:0] fill_addr,
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output reg invalidate_fill
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);
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`ifndef FILL_INVALIDATOR_ACTIVE
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assign invalidate_fill = 0;
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`else
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reg[`FILL_INVALIDAOR_SIZE-1:0] fills_active;
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reg[`FILL_INVALIDAOR_SIZE-1:0][31:0] fills_address;
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reg success_found;
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reg[(`vx_clog2(`FILL_INVALIDAOR_SIZE))-1:0] success_index;
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integer curr_fill;
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always @(*) begin
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invalidate_fill = 0;
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success_found = 0;
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success_index = 0;
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for (curr_fill = 0; curr_fill < `FILL_INVALIDAOR_SIZE; curr_fill=curr_fill+1) begin
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if (fill_addr[31:`LINE_SELECT_ADDR_START] == fills_address[curr_fill][31:`LINE_SELECT_ADDR_START]) begin
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if (possible_fill && fills_active[curr_fill]) begin
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invalidate_fill = 1;
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end
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if (success_fill) begin
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success_found = 1;
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success_index = curr_fill;
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end
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end
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end
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end
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wire [(`vx_clog2(`FILL_INVALIDAOR_SIZE))-1:0] enqueue_index;
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wire enqueue_found;
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VX_generic_priority_encoder #(.N(`FILL_INVALIDAOR_SIZE)) VX_sel_bank(
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.valids(fills_active),
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.index (enqueue_index),
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.found (enqueue_found)
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);
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reg[`FILL_INVALIDAOR_SIZE-1:0] new_valids;
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always @(posedge clk) begin
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if (reset) begin
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fills_active <= 0;
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fills_address <= 0;
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end else begin
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if (enqueue_found && !invalidate_fill) begin
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fills_active[enqueue_index] <= 1;
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fills_address[enqueue_index] <= fill_addr;
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end
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if (success_found) begin
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fills_active[success_index] <= 0;
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end
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end
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end
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`endif
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endmodule |