54 lines
2.4 KiB
Verilog
54 lines
2.4 KiB
Verilog
`include "VX_define.vh"
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module VX_l1c_to_dram_arb #(
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parameter REQQ_SIZE = 8
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) (
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input wire clk,
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input wire reset,
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VX_cache_dram_req_if dcache_dram_req_if,
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VX_cache_dram_rsp_if dcache_dram_rsp_if,
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VX_cache_dram_req_if icache_dram_req_if,
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VX_cache_dram_rsp_if icache_dram_rsp_if,
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VX_cache_dram_req_if dram_req_if,
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VX_cache_dram_rsp_if dram_rsp_if
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);
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reg cache_sel;
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wire icache_req_valid, icache_sel_out, icache_sel_in;
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assign icache_req_valid = icache_dram_req_if.dram_req_read || icache_dram_req_if.dram_req_write;
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assign icache_sel_out = icache_req_valid && (cache_sel == 0);
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assign dram_req_if.dram_req_read = icache_sel_out ? icache_dram_req_if.dram_req_read : dcache_dram_req_if.dram_req_read;
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assign dram_req_if.dram_req_write = icache_sel_out ? icache_dram_req_if.dram_req_write : dcache_dram_req_if.dram_req_write;
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assign dram_req_if.dram_req_addr = icache_sel_out ? icache_dram_req_if.dram_req_addr : dcache_dram_req_if.dram_req_addr;
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assign dram_req_if.dram_req_data = icache_sel_out ? icache_dram_req_if.dram_req_data : dcache_dram_req_if.dram_req_data;
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assign dram_req_if.dram_req_tag = {icache_sel_out ? icache_dram_req_if.dram_req_tag : dcache_dram_req_if.dram_req_tag, icache_sel_out};
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assign icache_dram_req_if.dram_req_ready = dram_req_if.dram_req_ready && (cache_sel == 0);
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assign dcache_dram_req_if.dram_req_ready = dram_req_if.dram_req_ready && (cache_sel == 1);
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assign icache_sel_in = dram_rsp_if.dram_rsp_tag[0];
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assign icache_dram_rsp_if.dram_rsp_valid = dram_rsp_if.dram_rsp_valid && icache_sel_in;
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assign icache_dram_rsp_if.dram_rsp_data = dram_rsp_if.dram_rsp_data;
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assign icache_dram_rsp_if.dram_rsp_tag = dram_rsp_if.dram_rsp_tag[1 +: $bits(icache_dram_rsp_if.dram_rsp_tag)];
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assign dcache_dram_rsp_if.dram_rsp_valid = dram_rsp_if.dram_rsp_valid && ~icache_sel_in;
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assign dcache_dram_rsp_if.dram_rsp_data = dram_rsp_if.dram_rsp_data;
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assign dcache_dram_rsp_if.dram_rsp_tag = dram_rsp_if.dram_rsp_tag[1 +: $bits(dcache_dram_rsp_if.dram_rsp_tag)];
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assign dram_rsp_if.dram_rsp_ready = icache_dram_rsp_if.dram_rsp_ready && dcache_dram_rsp_if.dram_rsp_ready;
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always @(posedge clk) begin
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if (reset) begin
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cache_sel <= 0;
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end else begin
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cache_sel <= ~cache_sel;
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end
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end
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endmodule |