c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
376 lines
14 KiB
Systemverilog
376 lines
14 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_stream_arb #(
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parameter NUM_INPUTS = 1,
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parameter NUM_OUTPUTS = 1,
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parameter DATAW = 1,
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parameter `STRING ARBITER = "P",
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parameter LOCK_ENABLE = 1,
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parameter MAX_FANOUT = `MAX_FANOUT,
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parameter OUT_REG = 0 ,
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parameter NUM_REQS = (NUM_INPUTS + NUM_OUTPUTS - 1) / NUM_OUTPUTS,
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parameter LOG_NUM_REQS = `CLOG2(NUM_REQS),
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parameter NUM_REQS_W = `UP(LOG_NUM_REQS)
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) (
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input wire clk,
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input wire reset,
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input wire [NUM_INPUTS-1:0] valid_in,
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input wire [NUM_INPUTS-1:0][DATAW-1:0] data_in,
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output wire [NUM_INPUTS-1:0] ready_in,
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output wire [NUM_OUTPUTS-1:0] valid_out,
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output wire [NUM_OUTPUTS-1:0][DATAW-1:0] data_out,
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output wire [NUM_OUTPUTS-1:0][NUM_REQS_W-1:0] sel_out,
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input wire [NUM_OUTPUTS-1:0] ready_out
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);
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if (NUM_INPUTS > NUM_OUTPUTS) begin
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if (NUM_OUTPUTS > 1) begin
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// (#inputs > #outputs) and (#outputs > 1)
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for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
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localparam BATCH_BEGIN = i * NUM_REQS;
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localparam BATCH_END = `MIN(BATCH_BEGIN + NUM_REQS, NUM_INPUTS);
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localparam BATCH_SIZE = BATCH_END - BATCH_BEGIN;
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`RESET_RELAY (slice_reset, reset);
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VX_stream_arb #(
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.NUM_INPUTS (BATCH_SIZE),
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.NUM_OUTPUTS (1),
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.DATAW (DATAW),
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.ARBITER (ARBITER),
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.LOCK_ENABLE (LOCK_ENABLE),
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.MAX_FANOUT (MAX_FANOUT),
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.OUT_REG (OUT_REG)
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) arb_slice (
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.clk (clk),
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.reset (slice_reset),
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.valid_in (valid_in[BATCH_END-1: BATCH_BEGIN]),
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.ready_in (ready_in[BATCH_END-1: BATCH_BEGIN]),
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.data_in (data_in[BATCH_END-1: BATCH_BEGIN]),
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.data_out (data_out[i]),
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.sel_out (sel_out[i]),
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.valid_out (valid_out[i]),
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.ready_out (ready_out[i])
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);
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end
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end else if (MAX_FANOUT != 0 && (NUM_INPUTS > (MAX_FANOUT + MAX_FANOUT/2))) begin
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// (#inputs > max_fanout) and (#outputs == 1)
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localparam NUM_BATCHES = (NUM_INPUTS + MAX_FANOUT - 1) / MAX_FANOUT;
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localparam LOG_NUM_REQS2 = `CLOG2(MAX_FANOUT);
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localparam LOG_NUM_REQS3 = `CLOG2(NUM_BATCHES);
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wire [NUM_BATCHES-1:0] valid_tmp;
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wire [NUM_BATCHES-1:0][DATAW+LOG_NUM_REQS2-1:0] data_tmp;
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wire [NUM_BATCHES-1:0] ready_tmp;
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for (genvar i = 0; i < NUM_BATCHES; ++i) begin
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localparam BATCH_BEGIN = i * MAX_FANOUT;
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localparam BATCH_END = `MIN(BATCH_BEGIN + MAX_FANOUT, NUM_INPUTS);
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localparam BATCH_SIZE = BATCH_END - BATCH_BEGIN;
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wire [DATAW-1:0] data_tmp_u;
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wire [`LOG2UP(BATCH_SIZE)-1:0] sel_tmp_u;
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`RESET_RELAY (slice_reset, reset);
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if (MAX_FANOUT != 1) begin
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VX_stream_arb #(
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.NUM_INPUTS (BATCH_SIZE),
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.NUM_OUTPUTS (1),
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.DATAW (DATAW),
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.ARBITER (ARBITER),
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.LOCK_ENABLE (LOCK_ENABLE),
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.MAX_FANOUT (MAX_FANOUT),
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.OUT_REG (OUT_REG)
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) fanout_slice_arb (
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.clk (clk),
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.reset (slice_reset),
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.valid_in (valid_in[BATCH_END-1: BATCH_BEGIN]),
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.data_in (data_in[BATCH_END-1: BATCH_BEGIN]),
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.ready_in (ready_in[BATCH_END-1: BATCH_BEGIN]),
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.valid_out (valid_tmp[i]),
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.data_out (data_tmp_u),
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.sel_out (sel_tmp_u),
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.ready_out (ready_tmp[i])
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);
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end
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assign data_tmp[i] = {data_tmp_u, LOG_NUM_REQS2'(sel_tmp_u)};
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end
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wire [DATAW+LOG_NUM_REQS2-1:0] data_out_u;
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wire [LOG_NUM_REQS3-1:0] sel_out_u;
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VX_stream_arb #(
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.NUM_INPUTS (NUM_BATCHES),
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.NUM_OUTPUTS (1),
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.DATAW (DATAW + LOG_NUM_REQS2),
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.ARBITER (ARBITER),
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.LOCK_ENABLE (LOCK_ENABLE),
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.MAX_FANOUT (MAX_FANOUT),
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.OUT_REG (OUT_REG)
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) fanout_join_arb (
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.clk (clk),
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.reset (reset),
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.valid_in (valid_tmp),
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.ready_in (ready_tmp),
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.data_in (data_tmp),
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.data_out (data_out_u),
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.sel_out (sel_out_u),
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.valid_out (valid_out),
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.ready_out (ready_out)
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);
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assign data_out = data_out_u[LOG_NUM_REQS2 +: DATAW];
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assign sel_out = {sel_out_u, data_out_u[0 +: LOG_NUM_REQS2]};
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end else begin
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// (#inputs <= max_fanout) and (#outputs == 1)
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wire valid_in_r;
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wire [DATAW-1:0] data_in_r;
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wire ready_in_r;
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wire arb_valid;
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wire [NUM_REQS_W-1:0] arb_index;
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wire [NUM_REQS-1:0] arb_onehot;
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wire arb_unlock;
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VX_generic_arbiter #(
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.NUM_REQS (NUM_REQS),
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.LOCK_ENABLE (LOCK_ENABLE),
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.TYPE (ARBITER)
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) arbiter (
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.clk (clk),
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.reset (reset),
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.requests (valid_in),
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.unlock (arb_unlock),
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.grant_valid (arb_valid),
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.grant_index (arb_index),
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.grant_onehot (arb_onehot)
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);
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assign valid_in_r = arb_valid;
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assign data_in_r = data_in[arb_index];
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assign arb_unlock = | (valid_in_r & ready_in_r);
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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assign ready_in[i] = ready_in_r & arb_onehot[i];
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end
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VX_elastic_buffer #(
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.DATAW (LOG_NUM_REQS + DATAW),
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.SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)),
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.OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG))
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) out_buf (
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.clk (clk),
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.reset (reset),
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.valid_in (valid_in_r),
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.ready_in (ready_in_r),
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.data_in ({arb_index, data_in_r}),
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.data_out ({sel_out, data_out}),
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.valid_out (valid_out),
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.ready_out (ready_out)
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);
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end
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end else if (NUM_OUTPUTS > NUM_INPUTS) begin
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if (NUM_INPUTS > 1) begin
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// (#inputs > 1) and (#outputs > #inputs)
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for (genvar i = 0; i < NUM_INPUTS; ++i) begin
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localparam BATCH_BEGIN = i * NUM_REQS;
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localparam BATCH_END = `MIN(BATCH_BEGIN + NUM_REQS, NUM_OUTPUTS);
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localparam BATCH_SIZE = BATCH_END - BATCH_BEGIN;
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`RESET_RELAY (slice_reset, reset);
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VX_stream_arb #(
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.NUM_INPUTS (1),
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.NUM_OUTPUTS (BATCH_SIZE),
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.DATAW (DATAW),
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.ARBITER (ARBITER),
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.LOCK_ENABLE (LOCK_ENABLE),
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.MAX_FANOUT (MAX_FANOUT),
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.OUT_REG (OUT_REG)
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) arb_slice (
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.clk (clk),
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.reset (slice_reset),
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.valid_in (valid_in[i]),
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.ready_in (ready_in[i]),
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.data_in (data_in[i]),
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.data_out (data_out[BATCH_END-1: BATCH_BEGIN]),
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.valid_out (valid_out[BATCH_END-1: BATCH_BEGIN]),
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.ready_out (ready_out[BATCH_END-1: BATCH_BEGIN]),
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`UNUSED_PIN (sel_out)
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);
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for (genvar j = BATCH_BEGIN; j < BATCH_END; ++j) begin
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assign sel_out[j] = i;
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end
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end
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end else if (MAX_FANOUT != 0 && (NUM_OUTPUTS > (MAX_FANOUT + MAX_FANOUT/2))) begin
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// (#inputs == 1) and (#outputs > max_fanout)
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localparam NUM_BATCHES = (NUM_OUTPUTS + MAX_FANOUT - 1) / MAX_FANOUT;
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wire [NUM_BATCHES-1:0] valid_tmp;
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wire [NUM_BATCHES-1:0][DATAW-1:0] data_tmp;
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wire [NUM_BATCHES-1:0] ready_tmp;
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VX_stream_arb #(
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.NUM_INPUTS (1),
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.NUM_OUTPUTS (NUM_BATCHES),
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.DATAW (DATAW),
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.ARBITER (ARBITER),
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.LOCK_ENABLE (LOCK_ENABLE),
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.MAX_FANOUT (MAX_FANOUT),
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.OUT_REG (OUT_REG)
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) fanout_fork_arb (
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.clk (clk),
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.reset (reset),
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.valid_in (valid_in),
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.ready_in (ready_in),
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.data_in (data_in),
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.data_out (data_tmp),
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.valid_out (valid_tmp),
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.ready_out (ready_tmp),
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`UNUSED_PIN (sel_out)
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);
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for (genvar i = 0; i < NUM_BATCHES; ++i) begin
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localparam BATCH_BEGIN = i * MAX_FANOUT;
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localparam BATCH_END = `MIN(BATCH_BEGIN + MAX_FANOUT, NUM_OUTPUTS);
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localparam BATCH_SIZE = BATCH_END - BATCH_BEGIN;
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`RESET_RELAY (slice_reset, reset);
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VX_stream_arb #(
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.NUM_INPUTS (1),
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.NUM_OUTPUTS (BATCH_SIZE),
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.DATAW (DATAW),
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.ARBITER (ARBITER),
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.LOCK_ENABLE (LOCK_ENABLE),
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.MAX_FANOUT (MAX_FANOUT),
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.OUT_REG (OUT_REG)
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) fanout_slice_arb (
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.clk (clk),
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.reset (slice_reset),
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.valid_in (valid_tmp[i]),
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.ready_in (ready_tmp[i]),
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.data_in (data_tmp[i]),
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.data_out (data_out[BATCH_END-1: BATCH_BEGIN]),
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.valid_out (valid_out[BATCH_END-1: BATCH_BEGIN]),
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.ready_out (ready_out[BATCH_END-1: BATCH_BEGIN]),
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`UNUSED_PIN (sel_out)
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);
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end
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end else begin
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// (#inputs == 1) and (#outputs <= max_fanout)
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wire [NUM_OUTPUTS-1:0] ready_in_r;
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wire [NUM_OUTPUTS-1:0] arb_requests;
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wire arb_valid;
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wire [NUM_OUTPUTS-1:0] arb_onehot;
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wire arb_unlock;
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VX_generic_arbiter #(
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.NUM_REQS (NUM_OUTPUTS),
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.LOCK_ENABLE (LOCK_ENABLE),
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.TYPE (ARBITER)
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) arbiter (
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.clk (clk),
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.reset (reset),
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.requests (arb_requests),
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.unlock (arb_unlock),
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.grant_valid (arb_valid),
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`UNUSED_PIN (grant_index),
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.grant_onehot (arb_onehot)
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);
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assign arb_requests = ready_in_r;
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assign arb_unlock = | (valid_in & ready_in);
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assign ready_in = arb_valid;
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for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
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VX_elastic_buffer #(
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.DATAW (DATAW),
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.SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)),
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.OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG))
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) out_buf (
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.clk (clk),
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.reset (reset),
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.valid_in (valid_in && arb_onehot[i]),
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.ready_in (ready_in_r[i]),
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.data_in (data_in),
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.data_out (data_out[i]),
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.valid_out (valid_out[i]),
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.ready_out (ready_out[i])
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);
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end
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end
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assign sel_out = 0;
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end else begin
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// #Inputs == #Outputs
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for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
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`RESET_RELAY_EN (out_buf_reset, reset, (NUM_OUTPUTS > 1));
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VX_elastic_buffer #(
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.DATAW (DATAW),
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.SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)),
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.OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG))
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) out_buf (
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.clk (clk),
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.reset (out_buf_reset),
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.valid_in (valid_in[i]),
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.ready_in (ready_in[i]),
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.data_in (data_in[i]),
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.data_out (data_out[i]),
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.valid_out (valid_out[i]),
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.ready_out (ready_out[i])
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);
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assign sel_out[i] = NUM_REQS_W'(i);
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end
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end
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endmodule
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`TRACING_ON
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