c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
225 lines
7.8 KiB
Systemverilog
225 lines
7.8 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_popcount63(
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input wire [5:0] data_in,
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output wire [2:0] data_out
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);
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reg [2:0] sum;
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always @(*) begin
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case (data_in)
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6'd0: sum=3'd0; 6'd1: sum=3'd1; 6'd2: sum=3'd1; 6'd3: sum=3'd2;
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6'd4: sum=3'd1; 6'd5: sum=3'd2; 6'd6: sum=3'd2; 6'd7: sum=3'd3;
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6'd8: sum=3'd1; 6'd9: sum=3'd2; 6'd10: sum=3'd2; 6'd11: sum=3'd3;
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6'd12: sum=3'd2; 6'd13: sum=3'd3; 6'd14: sum=3'd3; 6'd15: sum=3'd4;
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6'd16: sum=3'd1; 6'd17: sum=3'd2; 6'd18: sum=3'd2; 6'd19: sum=3'd3;
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6'd20: sum=3'd2; 6'd21: sum=3'd3; 6'd22: sum=3'd3; 6'd23: sum=3'd4;
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6'd24: sum=3'd2; 6'd25: sum=3'd3; 6'd26: sum=3'd3; 6'd27: sum=3'd4;
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6'd28: sum=3'd3; 6'd29: sum=3'd4; 6'd30: sum=3'd4; 6'd31: sum=3'd5;
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6'd32: sum=3'd1; 6'd33: sum=3'd2; 6'd34: sum=3'd2; 6'd35: sum=3'd3;
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6'd36: sum=3'd2; 6'd37: sum=3'd3; 6'd38: sum=3'd3; 6'd39: sum=3'd4;
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6'd40: sum=3'd2; 6'd41: sum=3'd3; 6'd42: sum=3'd3; 6'd43: sum=3'd4;
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6'd44: sum=3'd3; 6'd45: sum=3'd4; 6'd46: sum=3'd4; 6'd47: sum=3'd5;
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6'd48: sum=3'd2; 6'd49: sum=3'd3; 6'd50: sum=3'd3; 6'd51: sum=3'd4;
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6'd52: sum=3'd3; 6'd53: sum=3'd4; 6'd54: sum=3'd4; 6'd55: sum=3'd5;
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6'd56: sum=3'd3; 6'd57: sum=3'd4; 6'd58: sum=3'd4; 6'd59: sum=3'd5;
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6'd60: sum=3'd4; 6'd61: sum=3'd5; 6'd62: sum=3'd5; 6'd63: sum=3'd6;
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endcase
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end
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assign data_out = sum;
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endmodule
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module VX_popcount32(
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input wire [2:0] data_in,
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output wire [1:0] data_out
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);
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reg [1:0] sum;
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always @(*) begin
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case (data_in)
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3'd0: sum=2'd0; 3'd1: sum=2'd1; 3'd2: sum=2'd1; 3'd3: sum=2'd2;
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3'd4: sum=2'd1; 3'd5: sum=2'd2; 3'd6: sum=2'd2; 3'd7: sum=2'd3;
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endcase
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end
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assign data_out = sum;
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endmodule
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module VX_sum33(
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input wire [2:0] data_in1,
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input wire [2:0] data_in2,
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output wire [3:0] data_out
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);
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reg [3:0] sum;
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always @(*) begin
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case ({data_in1, data_in2})
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6'd0: sum=4'd0; 6'd1: sum=4'd1; 6'd2: sum=4'd2; 6'd3: sum=4'd3;
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6'd4: sum=4'd4; 6'd5: sum=4'd5; 6'd6: sum=4'd6; 6'd7: sum=4'd7;
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6'd8: sum=4'd1; 6'd9: sum=4'd2; 6'd10: sum=4'd3; 6'd11: sum=4'd4;
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6'd12: sum=4'd5; 6'd13: sum=4'd6; 6'd14: sum=4'd7; 6'd15: sum=4'd8;
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6'd16: sum=4'd2; 6'd17: sum=4'd3; 6'd18: sum=4'd4; 6'd19: sum=4'd5;
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6'd20: sum=4'd6; 6'd21: sum=4'd7; 6'd22: sum=4'd8; 6'd23: sum=4'd9;
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6'd24: sum=4'd3; 6'd25: sum=4'd4; 6'd26: sum=4'd5; 6'd27: sum=4'd6;
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6'd28: sum=4'd7; 6'd29: sum=4'd8; 6'd30: sum=4'd9; 6'd31: sum=4'd10;
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6'd32: sum=4'd4; 6'd33: sum=4'd5; 6'd34: sum=4'd6; 6'd35: sum=4'd7;
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6'd36: sum=4'd8; 6'd37: sum=4'd9; 6'd38: sum=4'd10; 6'd39: sum=4'd11;
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6'd40: sum=4'd5; 6'd41: sum=4'd6; 6'd42: sum=4'd7; 6'd43: sum=4'd8;
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6'd44: sum=4'd9; 6'd45: sum=4'd10; 6'd46: sum=4'd11; 6'd47: sum=4'd12;
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6'd48: sum=4'd6; 6'd49: sum=4'd7; 6'd50: sum=4'd8; 6'd51: sum=4'd9;
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6'd52: sum=4'd10; 6'd53: sum=4'd11; 6'd54: sum=4'd12; 6'd55: sum=4'd13;
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6'd56: sum=4'd7; 6'd57: sum=4'd8; 6'd58: sum=4'd9; 6'd59: sum=4'd10;
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6'd60: sum=4'd11; 6'd61: sum=4'd12; 6'd62: sum=4'd13; 6'd63: sum=4'd14;
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endcase
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end
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assign data_out = sum;
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endmodule
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module VX_popcount #(
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parameter MODEL = 1,
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parameter N = 1,
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parameter M = `CLOG2(N+1)
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) (
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input wire [N-1:0] data_in,
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output wire [M-1:0] data_out
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);
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`UNUSED_PARAM (MODEL)
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`ifndef SYNTHESIS
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assign data_out = $countones(data_in);
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`elsif QUARTUS
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assign data_out = $countones(data_in);
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`else
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if (N == 1) begin
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assign data_out = data_in;
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end else if (N <= 3) begin
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reg [2:0] t_in;
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wire [1:0] t_out;
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always @(*) begin
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t_in = '0;
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t_in[N-1:0] = data_in;
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end
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VX_popcount32 pc32(t_in, t_out);
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assign data_out = t_out[M-1:0];
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end else if (N <= 6) begin
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reg [5:0] t_in;
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wire [2:0] t_out;
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always @(*) begin
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t_in = '0;
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t_in[N-1:0] = data_in;
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end
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VX_popcount63 pc63(t_in, t_out);
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assign data_out = t_out[M-1:0];
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end else if (N <= 9) begin
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reg [8:0] t_in;
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wire [4:0] t1_out;
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wire [3:0] t2_out;
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always @(*) begin
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t_in = '0;
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t_in[N-1:0] = data_in;
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end
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VX_popcount63 pc63(t_in[5:0], t1_out[2:0]);
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VX_popcount32 pc32(t_in[8:6], t1_out[4:3]);
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VX_sum33 sum33(t1_out[2:0], {1'b0, t1_out[4:3]}, t2_out);
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assign data_out = t2_out[M-1:0];
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end else if (N <= 12) begin
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reg [11:0] t_in;
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wire [5:0] t1_out;
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wire [3:0] t2_out;
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always @(*) begin
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t_in = '0;
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t_in[N-1:0] = data_in;
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end
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VX_popcount63 pc63a(t_in[5:0], t1_out[2:0]);
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VX_popcount63 pc63b(t_in[11:6], t1_out[5:3]);
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VX_sum33 sum33(t1_out[2:0], t1_out[5:3], t2_out);
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assign data_out = t2_out[M-1:0];
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end else if (N <= 18) begin
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reg [17:0] t_in;
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wire [8:0] t1_out;
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wire [5:0] t2_out;
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always @(*) begin
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t_in = '0;
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t_in[N-1:0] = data_in;
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end
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VX_popcount63 pc63a(t_in[5:0], t1_out[2:0]);
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VX_popcount63 pc63b(t_in[11:6], t1_out[5:3]);
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VX_popcount63 pc63c(t_in[17:12], t1_out[8:6]);
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VX_popcount32 pc32a({t1_out[0], t1_out[3], t1_out[6]}, t2_out[1:0]);
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VX_popcount32 pc32b({t1_out[1], t1_out[4], t1_out[7]}, t2_out[3:2]);
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VX_popcount32 pc32c({t1_out[2], t1_out[5], t1_out[8]}, t2_out[5:4]);
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assign data_out = {2'b0,t2_out[1:0]} + {1'b0,t2_out[3:2],1'b0} + {t2_out[5:4],2'b0};
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end else if (MODEL == 1) begin
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localparam PN = 1 << `CLOG2(N);
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localparam LOGPN = `CLOG2(PN);
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`IGNORE_UNOPTFLAT_BEGIN
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wire [M-1:0] tmp [LOGPN-1:0][PN-1:0];
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`IGNORE_UNOPTFLAT_END
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for (genvar j = 0; j < LOGPN; ++j) begin
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localparam D = j + 1;
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localparam Q = (D < LOGPN) ? (D + 1) : M;
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for (genvar i = 0; i < (1 << (LOGPN-j-1)); ++i) begin
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localparam l = i * 2;
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localparam r = i * 2 + 1;
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wire [Q-1:0] res;
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if (j == 0) begin
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if (r < N) begin
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assign res = data_in[l] + data_in[r];
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end else if (l < N) begin
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assign res = 2'(data_in[l]);
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end else begin
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assign res = 2'b0;
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end
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end else begin
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assign res = D'(tmp[j-1][l]) + D'(tmp[j-1][r]);
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end
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assign tmp[j][i] = M'(res);
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end
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end
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assign data_out = tmp[LOGPN-1][0];
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end else begin
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reg [M-1:0] cnt_r;
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always @(*) begin
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cnt_r = '0;
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for (integer i = 0; i < N; ++i) begin
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cnt_r = cnt_r + M'(data_in[i]);
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end
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end
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assign data_out = cnt_r;
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end
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`endif
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endmodule
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`TRACING_ON
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