c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
64 lines
2.0 KiB
Systemverilog
64 lines
2.0 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_bypass_buffer #(
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parameter DATAW = 1,
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parameter PASSTHRU = 0
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) (
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input wire clk,
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input wire reset,
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input wire valid_in,
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output wire ready_in,
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input wire [DATAW-1:0] data_in,
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output wire [DATAW-1:0] data_out,
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input wire ready_out,
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output wire valid_out
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);
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if (PASSTHRU != 0) begin
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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assign ready_in = ready_out;
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assign valid_out = valid_in;
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assign data_out = data_in;
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end else begin
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reg [DATAW-1:0] buffer;
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reg buffer_valid;
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always @(posedge clk) begin
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if (reset) begin
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buffer_valid <= 0;
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end else begin
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if (ready_out) begin
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buffer_valid <= 0;
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end
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if (valid_in && ~ready_out) begin
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`ASSERT(!buffer_valid, ("runtime error"));
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buffer_valid <= 1;
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end
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end
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if (valid_in && ~ready_out) begin
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buffer <= data_in;
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end
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end
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assign ready_in = ready_out || !buffer_valid;
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assign data_out = buffer_valid ? buffer : data_in;
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assign valid_out = valid_in || buffer_valid;
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end
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endmodule
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`TRACING_ON |