c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
53 lines
1.8 KiB
Systemverilog
53 lines
1.8 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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interface VX_dispatch_if import VX_gpu_pkg::*; ();
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// warning: this layout should not be modified without updating VX_dispatch_unit!!!
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typedef struct packed {
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logic [`UUID_WIDTH-1:0] uuid;
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logic [ISSUE_WIS_W-1:0] wis;
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logic [`NUM_THREADS-1:0] tmask;
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logic [`INST_ALU_BITS-1:0] op_type;
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logic [`INST_MOD_BITS-1:0] op_mod;
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logic wb;
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logic use_PC;
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logic use_imm;
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logic [`XLEN-1:0] PC;
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logic [`XLEN-1:0] imm;
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logic [`NR_BITS-1:0] rd;
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logic [`NT_WIDTH-1:0] tid;
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logic [`NUM_THREADS-1:0][`XLEN-1:0] rs1_data;
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logic [`NUM_THREADS-1:0][`XLEN-1:0] rs2_data;
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logic [`NUM_THREADS-1:0][`XLEN-1:0] rs3_data;
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} data_t;
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logic valid;
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data_t data;
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logic ready;
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modport master (
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output valid,
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output data,
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input ready
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);
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modport slave (
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input valid,
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input data,
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output ready
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);
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endinterface
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