c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
307 lines
17 KiB
Systemverilog
307 lines
17 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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`ifdef EXT_F_ENABLE
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`include "VX_fpu_define.vh"
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`endif
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module VX_csr_data
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import VX_gpu_pkg::*;
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`ifdef EXT_F_ENABLE
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import VX_fpu_pkg::*;
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`endif
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#(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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input base_dcrs_t base_dcrs,
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`ifdef PERF_ENABLE
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VX_mem_perf_if.slave mem_perf_if,
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VX_pipeline_perf_if.slave pipeline_perf_if,
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VX_sfu_perf_if.slave sfu_perf_if,
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`endif
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VX_commit_csr_if.slave commit_csr_if,
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`ifdef EXT_F_ENABLE
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VX_fpu_to_csr_if.slave fpu_to_csr_if [`NUM_FPU_BLOCKS],
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`endif
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input wire [`PERF_CTR_BITS-1:0] cycles,
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input wire [`NUM_WARPS-1:0] active_warps,
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input wire [`NUM_WARPS-1:0][`NUM_THREADS-1:0] thread_masks,
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input wire read_enable,
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input wire [`UUID_WIDTH-1:0] read_uuid,
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input wire [`NW_WIDTH-1:0] read_wid,
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input wire [`VX_CSR_ADDR_BITS-1:0] read_addr,
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output wire [31:0] read_data_ro,
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output wire [31:0] read_data_rw,
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input wire write_enable,
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input wire [`UUID_WIDTH-1:0] write_uuid,
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input wire [`NW_WIDTH-1:0] write_wid,
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input wire [`VX_CSR_ADDR_BITS-1:0] write_addr,
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input wire [31:0] write_data
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);
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`UNUSED_VAR (reset)
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`UNUSED_VAR (write_wid)
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`UNUSED_VAR (write_data)
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// CSRs Write /////////////////////////////////////////////////////////////
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`ifdef EXT_F_ENABLE
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reg [`NUM_WARPS-1:0][`INST_FRM_BITS+`FP_FLAGS_BITS-1:0] fcsr, fcsr_n;
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wire [`NUM_FPU_BLOCKS-1:0] fpu_write_enable;
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wire [`NUM_FPU_BLOCKS-1:0][`NW_WIDTH-1:0] fpu_write_wid;
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fflags_t [`NUM_FPU_BLOCKS-1:0] fpu_write_fflags;
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for (genvar i = 0; i < `NUM_FPU_BLOCKS; ++i) begin
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assign fpu_write_enable[i] = fpu_to_csr_if[i].write_enable;
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assign fpu_write_wid[i] = fpu_to_csr_if[i].write_wid;
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assign fpu_write_fflags[i] = fpu_to_csr_if[i].write_fflags;
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end
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always @(*) begin
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fcsr_n = fcsr;
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for (integer i = 0; i < `NUM_FPU_BLOCKS; ++i) begin
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if (fpu_write_enable[i]) begin
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fcsr_n[fpu_write_wid[i]][`FP_FLAGS_BITS-1:0] = fcsr[fpu_write_wid[i]][`FP_FLAGS_BITS-1:0]
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| fpu_write_fflags[i];
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end
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end
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if (write_enable) begin
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case (write_addr)
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`VX_CSR_FFLAGS: fcsr_n[write_wid][`FP_FLAGS_BITS-1:0] = write_data[`FP_FLAGS_BITS-1:0];
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`VX_CSR_FRM: fcsr_n[write_wid][`INST_FRM_BITS+`FP_FLAGS_BITS-1:`FP_FLAGS_BITS] = write_data[`INST_FRM_BITS-1:0];
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`VX_CSR_FCSR: fcsr_n[write_wid] = write_data[`FP_FLAGS_BITS+`INST_FRM_BITS-1:0];
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default:;
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endcase
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end
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end
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for (genvar i = 0; i < `NUM_FPU_BLOCKS; ++i) begin
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assign fpu_to_csr_if[i].read_frm = fcsr[fpu_to_csr_if[i].read_wid][`INST_FRM_BITS+`FP_FLAGS_BITS-1:`FP_FLAGS_BITS];
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end
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always @(posedge clk) begin
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if (reset) begin
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fcsr <= '0;
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end else begin
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fcsr <= fcsr_n;
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end
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end
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`endif
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always @(posedge clk) begin
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if (write_enable) begin
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case (write_addr)
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`ifdef EXT_F_ENABLE
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`VX_CSR_FFLAGS,
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`VX_CSR_FRM,
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`VX_CSR_FCSR,
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`endif
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`VX_CSR_SATP,
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`VX_CSR_MSTATUS,
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`VX_CSR_MNSTATUS,
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`VX_CSR_MEDELEG,
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`VX_CSR_MIDELEG,
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`VX_CSR_MIE,
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`VX_CSR_MTVEC,
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`VX_CSR_MEPC,
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`VX_CSR_PMPCFG0,
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`VX_CSR_PMPADDR0: /* do nothing!*/;
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default: begin
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`ASSERT(0, ("%t: *** invalid CSR write address: %0h (#%0d)", $time, write_addr, write_uuid));
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end
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endcase
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end
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end
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// CSRs read //////////////////////////////////////////////////////////////
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reg [31:0] read_data_ro_r;
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reg [31:0] read_data_rw_r;
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reg read_addr_valid_r;
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always @(*) begin
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read_data_ro_r = '0;
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read_data_rw_r = '0;
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read_addr_valid_r = 1;
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case (read_addr)
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`VX_CSR_MVENDORID : read_data_ro_r = 32'(`VENDOR_ID);
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`VX_CSR_MARCHID : read_data_ro_r = 32'(`ARCHITECTURE_ID);
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`VX_CSR_MIMPID : read_data_ro_r = 32'(`IMPLEMENTATION_ID);
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`VX_CSR_MISA : read_data_ro_r = (((`CLOG2(`XLEN)-4) << (`XLEN-2)) | `MISA_STD);
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`ifdef EXT_F_ENABLE
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`VX_CSR_FFLAGS : read_data_rw_r = 32'(fcsr[read_wid][`FP_FLAGS_BITS-1:0]);
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`VX_CSR_FRM : read_data_rw_r = 32'(fcsr[read_wid][`INST_FRM_BITS+`FP_FLAGS_BITS-1:`FP_FLAGS_BITS]);
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`VX_CSR_FCSR : read_data_rw_r = 32'(fcsr[read_wid]);
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`endif
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`VX_CSR_WARP_ID : read_data_ro_r = 32'(read_wid);
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`VX_CSR_CORE_ID : read_data_ro_r = 32'(CORE_ID);
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`VX_CSR_THREAD_MASK: read_data_ro_r = 32'(thread_masks[read_wid]);
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`VX_CSR_WARP_MASK : read_data_ro_r = 32'(active_warps);
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`VX_CSR_NUM_THREADS: read_data_ro_r = 32'(`NUM_THREADS);
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`VX_CSR_NUM_WARPS : read_data_ro_r = 32'(`NUM_WARPS);
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`VX_CSR_NUM_CORES : read_data_ro_r = 32'(`NUM_CORES * `NUM_CLUSTERS);
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`VX_CSR_MCYCLE : read_data_ro_r = 32'(cycles[31:0]);
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`VX_CSR_MCYCLE_H : read_data_ro_r = 32'(cycles[`PERF_CTR_BITS-1:32]);
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`VX_CSR_MPM_RESERVED : read_data_ro_r = 'x;
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`VX_CSR_MPM_RESERVED_H : read_data_ro_r = 'x;
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`VX_CSR_MINSTRET : read_data_ro_r = 32'(commit_csr_if.instret[31:0]);
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`VX_CSR_MINSTRET_H : read_data_ro_r = 32'(commit_csr_if.instret[`PERF_CTR_BITS-1:32]);
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`VX_CSR_SATP,
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`VX_CSR_MSTATUS,
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`VX_CSR_MNSTATUS,
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`VX_CSR_MEDELEG,
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`VX_CSR_MIDELEG,
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`VX_CSR_MIE,
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`VX_CSR_MTVEC,
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`VX_CSR_MEPC,
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`VX_CSR_PMPCFG0,
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`VX_CSR_PMPADDR0 : read_data_ro_r = 32'(0);
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default: begin
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read_addr_valid_r = 0;
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if ((read_addr >= `VX_CSR_MPM_BASE && read_addr < (`VX_CSR_MPM_BASE + 32))
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|| (read_addr >= `VX_CSR_MPM_BASE_H && read_addr < (`VX_CSR_MPM_BASE_H + 32))) begin
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read_addr_valid_r = 1;
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`ifdef PERF_ENABLE
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case (base_dcrs.mpm_class)
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`VX_DCR_MPM_CLASS_CORE: begin
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case (read_addr)
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// PERF: pipeline
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`VX_CSR_MPM_IBUF_ST : read_data_ro_r = pipeline_perf_if.ibf_stalls[31:0];
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`VX_CSR_MPM_IBUF_ST_H : read_data_ro_r = 32'(pipeline_perf_if.ibf_stalls[`PERF_CTR_BITS-1:32]);
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`VX_CSR_MPM_SCRB_ST : read_data_ro_r = pipeline_perf_if.scb_stalls[31:0];
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`VX_CSR_MPM_SCRB_ST_H : read_data_ro_r = 32'(pipeline_perf_if.scb_stalls[`PERF_CTR_BITS-1:32]);
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`VX_CSR_MPM_ALU_ST : read_data_ro_r = pipeline_perf_if.dsp_stalls[`EX_ALU][31:0];
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`VX_CSR_MPM_ALU_ST_H : read_data_ro_r = 32'(pipeline_perf_if.dsp_stalls[`EX_ALU][`PERF_CTR_BITS-1:32]);
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`VX_CSR_MPM_LSU_ST : read_data_ro_r = pipeline_perf_if.dsp_stalls[`EX_LSU][31:0];
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`VX_CSR_MPM_LSU_ST_H : read_data_ro_r = 32'(pipeline_perf_if.dsp_stalls[`EX_LSU][`PERF_CTR_BITS-1:32]);
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`ifdef EXT_F_ENABLE
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`VX_CSR_MPM_FPU_ST : read_data_ro_r = pipeline_perf_if.dsp_stalls[`EX_FPU][31:0];
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`VX_CSR_MPM_FPU_ST_H : read_data_ro_r = 32'(pipeline_perf_if.dsp_stalls[`EX_FPU][`PERF_CTR_BITS-1:32]);
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`else
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`VX_CSR_MPM_FPU_ST : read_data_ro_r = '0;
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`VX_CSR_MPM_FPU_ST_H : read_data_ro_r = '0;
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`endif
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`VX_CSR_MPM_SFU_ST : read_data_ro_r = pipeline_perf_if.dsp_stalls[`EX_SFU][31:0];
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`VX_CSR_MPM_SFU_ST_H : read_data_ro_r = 32'(pipeline_perf_if.dsp_stalls[`EX_SFU][`PERF_CTR_BITS-1:32]);
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// PERF: memory
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`VX_CSR_MPM_IFETCHES : read_data_ro_r = pipeline_perf_if.ifetches[31:0];
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`VX_CSR_MPM_IFETCHES_H : read_data_ro_r = 32'(pipeline_perf_if.ifetches[`PERF_CTR_BITS-1:32]);
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`VX_CSR_MPM_LOADS : read_data_ro_r = pipeline_perf_if.loads[31:0];
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`VX_CSR_MPM_LOADS_H : read_data_ro_r = 32'(pipeline_perf_if.loads[`PERF_CTR_BITS-1:32]);
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`VX_CSR_MPM_STORES : read_data_ro_r = pipeline_perf_if.stores[31:0];
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`VX_CSR_MPM_STORES_H : read_data_ro_r = 32'(pipeline_perf_if.stores[`PERF_CTR_BITS-1:32]);
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`VX_CSR_MPM_IFETCH_LAT : read_data_ro_r = pipeline_perf_if.ifetch_latency[31:0];
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`VX_CSR_MPM_IFETCH_LAT_H : read_data_ro_r = 32'(pipeline_perf_if.ifetch_latency[`PERF_CTR_BITS-1:32]);
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`VX_CSR_MPM_LOAD_LAT : read_data_ro_r = pipeline_perf_if.load_latency[31:0];
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`VX_CSR_MPM_LOAD_LAT_H : read_data_ro_r = 32'(pipeline_perf_if.load_latency[`PERF_CTR_BITS-1:32]);
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default:;
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endcase
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end
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`VX_DCR_MPM_CLASS_MEM: begin
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case (read_addr)
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// PERF: icache
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`VX_CSR_MPM_ICACHE_READS : read_data_ro_r = mem_perf_if.icache.reads[31:0];
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`VX_CSR_MPM_ICACHE_READS_H : read_data_ro_r = 32'(mem_perf_if.icache.reads[`PERF_CTR_BITS-1:32]);
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`VX_CSR_MPM_ICACHE_MISS_R : read_data_ro_r = mem_perf_if.icache.read_misses[31:0];
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`VX_CSR_MPM_ICACHE_MISS_R_H : read_data_ro_r = 32'(mem_perf_if.icache.read_misses[`PERF_CTR_BITS-1:32]);
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// PERF: dcache
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`VX_CSR_MPM_DCACHE_READS : read_data_ro_r = mem_perf_if.dcache.reads[31:0];
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`VX_CSR_MPM_DCACHE_READS_H : read_data_ro_r = 32'(mem_perf_if.dcache.reads[`PERF_CTR_BITS-1:32]);
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`VX_CSR_MPM_DCACHE_WRITES : read_data_ro_r = mem_perf_if.dcache.writes[31:0];
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`VX_CSR_MPM_DCACHE_WRITES_H : read_data_ro_r = 32'(mem_perf_if.dcache.writes[`PERF_CTR_BITS-1:32]);
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`VX_CSR_MPM_DCACHE_MISS_R : read_data_ro_r = mem_perf_if.dcache.read_misses[31:0];
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`VX_CSR_MPM_DCACHE_MISS_R_H : read_data_ro_r = 32'(mem_perf_if.dcache.read_misses[`PERF_CTR_BITS-1:32]);
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`VX_CSR_MPM_DCACHE_MISS_W : read_data_ro_r = mem_perf_if.dcache.write_misses[31:0];
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`VX_CSR_MPM_DCACHE_MISS_W_H : read_data_ro_r = 32'(mem_perf_if.dcache.write_misses[`PERF_CTR_BITS-1:32]);
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`VX_CSR_MPM_DCACHE_BANK_ST : read_data_ro_r = mem_perf_if.dcache.bank_stalls[31:0];
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`VX_CSR_MPM_DCACHE_BANK_ST_H : read_data_ro_r = 32'(mem_perf_if.dcache.bank_stalls[`PERF_CTR_BITS-1:32]);
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`VX_CSR_MPM_DCACHE_MSHR_ST : read_data_ro_r = mem_perf_if.dcache.mshr_stalls[31:0];
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`VX_CSR_MPM_DCACHE_MSHR_ST_H : read_data_ro_r = 32'(mem_perf_if.dcache.mshr_stalls[`PERF_CTR_BITS-1:32]);
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// PERF: smem
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`VX_CSR_MPM_SMEM_READS : read_data_ro_r = mem_perf_if.smem.reads[31:0];
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`VX_CSR_MPM_SMEM_READS_H : read_data_ro_r = 32'(mem_perf_if.smem.reads[`PERF_CTR_BITS-1:32]);
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`VX_CSR_MPM_SMEM_WRITES : read_data_ro_r = mem_perf_if.smem.writes[31:0];
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`VX_CSR_MPM_SMEM_WRITES_H : read_data_ro_r = 32'(mem_perf_if.smem.writes[`PERF_CTR_BITS-1:32]);
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`VX_CSR_MPM_SMEM_BANK_ST : read_data_ro_r = mem_perf_if.smem.bank_stalls[31:0];
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`VX_CSR_MPM_SMEM_BANK_ST_H : read_data_ro_r = 32'(mem_perf_if.smem.bank_stalls[`PERF_CTR_BITS-1:32]);
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// PERF: l2cache
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`VX_CSR_MPM_L2CACHE_READS : read_data_ro_r = mem_perf_if.l2cache.reads[31:0];
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`VX_CSR_MPM_L2CACHE_READS_H : read_data_ro_r = 32'(mem_perf_if.l2cache.reads[`PERF_CTR_BITS-1:32]);
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`VX_CSR_MPM_L2CACHE_WRITES : read_data_ro_r = mem_perf_if.l2cache.writes[31:0];
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`VX_CSR_MPM_L2CACHE_WRITES_H : read_data_ro_r = 32'(mem_perf_if.l2cache.writes[`PERF_CTR_BITS-1:32]);
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`VX_CSR_MPM_L2CACHE_MISS_R : read_data_ro_r = mem_perf_if.l2cache.read_misses[31:0];
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`VX_CSR_MPM_L2CACHE_MISS_R_H : read_data_ro_r = 32'(mem_perf_if.l2cache.read_misses[`PERF_CTR_BITS-1:32]);
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`VX_CSR_MPM_L2CACHE_MISS_W : read_data_ro_r = mem_perf_if.l2cache.write_misses[31:0];
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`VX_CSR_MPM_L2CACHE_MISS_W_H : read_data_ro_r = 32'(mem_perf_if.l2cache.write_misses[`PERF_CTR_BITS-1:32]);
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`VX_CSR_MPM_L2CACHE_BANK_ST : read_data_ro_r = mem_perf_if.l2cache.bank_stalls[31:0];
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`VX_CSR_MPM_L2CACHE_BANK_ST_H : read_data_ro_r = 32'(mem_perf_if.l2cache.bank_stalls[`PERF_CTR_BITS-1:32]);
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`VX_CSR_MPM_L2CACHE_MSHR_ST : read_data_ro_r = mem_perf_if.l2cache.mshr_stalls[31:0];
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`VX_CSR_MPM_L2CACHE_MSHR_ST_H : read_data_ro_r = 32'(mem_perf_if.l2cache.mshr_stalls[`PERF_CTR_BITS-1:32]);
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// PERF: l3cache
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`VX_CSR_MPM_L3CACHE_READS : read_data_ro_r = mem_perf_if.l3cache.reads[31:0];
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`VX_CSR_MPM_L3CACHE_READS_H : read_data_ro_r = 32'(mem_perf_if.l3cache.reads[`PERF_CTR_BITS-1:32]);
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`VX_CSR_MPM_L3CACHE_WRITES : read_data_ro_r = mem_perf_if.l3cache.writes[31:0];
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`VX_CSR_MPM_L3CACHE_WRITES_H : read_data_ro_r = 32'(mem_perf_if.l3cache.writes[`PERF_CTR_BITS-1:32]);
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`VX_CSR_MPM_L3CACHE_MISS_R : read_data_ro_r = mem_perf_if.l3cache.read_misses[31:0];
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`VX_CSR_MPM_L3CACHE_MISS_R_H : read_data_ro_r = 32'(mem_perf_if.l3cache.read_misses[`PERF_CTR_BITS-1:32]);
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`VX_CSR_MPM_L3CACHE_MISS_W : read_data_ro_r = mem_perf_if.l3cache.write_misses[31:0];
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`VX_CSR_MPM_L3CACHE_MISS_W_H : read_data_ro_r = 32'(mem_perf_if.l3cache.write_misses[`PERF_CTR_BITS-1:32]);
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`VX_CSR_MPM_L3CACHE_BANK_ST : read_data_ro_r = mem_perf_if.l3cache.bank_stalls[31:0];
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`VX_CSR_MPM_L3CACHE_BANK_ST_H : read_data_ro_r = 32'(mem_perf_if.l3cache.bank_stalls[`PERF_CTR_BITS-1:32]);
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`VX_CSR_MPM_L3CACHE_MSHR_ST : read_data_ro_r = mem_perf_if.l3cache.mshr_stalls[31:0];
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`VX_CSR_MPM_L3CACHE_MSHR_ST_H : read_data_ro_r = 32'(mem_perf_if.l3cache.mshr_stalls[`PERF_CTR_BITS-1:32]);
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// PERF: memory
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`VX_CSR_MPM_MEM_READS : read_data_ro_r = mem_perf_if.mem.reads[31:0];
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`VX_CSR_MPM_MEM_READS_H : read_data_ro_r = 32'(mem_perf_if.mem.reads[`PERF_CTR_BITS-1:32]);
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`VX_CSR_MPM_MEM_WRITES : read_data_ro_r = mem_perf_if.mem.writes[31:0];
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`VX_CSR_MPM_MEM_WRITES_H : read_data_ro_r = 32'(mem_perf_if.mem.writes[`PERF_CTR_BITS-1:32]);
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`VX_CSR_MPM_MEM_LAT : read_data_ro_r = mem_perf_if.mem.latency[31:0];
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`VX_CSR_MPM_MEM_LAT_H : read_data_ro_r = 32'(mem_perf_if.mem.latency[`PERF_CTR_BITS-1:32]);
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default:;
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endcase
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end
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default:;
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endcase
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`endif
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end
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end
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endcase
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end
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assign read_data_ro = read_data_ro_r;
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assign read_data_rw = read_data_rw_r;
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`UNUSED_VAR (base_dcrs)
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`RUNTIME_ASSERT(~read_enable || read_addr_valid_r, ("%t: *** invalid CSR read address: 0x%0h (#%0d)", $time, read_addr, read_uuid))
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`ifdef PERF_ENABLE
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wire [`PERF_CTR_BITS-1:0] perf_wctl_stalls = sfu_perf_if.wctl_stalls;
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`UNUSED_VAR (perf_wctl_stalls);
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`UNUSED_VAR (mem_perf_if.icache);
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`UNUSED_VAR (mem_perf_if.smem);
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`endif
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endmodule
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