c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
337 lines
10 KiB
Systemverilog
337 lines
10 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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`ifdef EXT_F_ENABLE
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`include "VX_fpu_define.vh"
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`endif
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module VX_core import VX_gpu_pkg::*; #(
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parameter CORE_ID = 0
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) (
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`SCOPE_IO_DECL
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// Clock
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input wire clk,
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input wire reset,
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`ifdef PERF_ENABLE
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VX_mem_perf_if.slave mem_perf_if,
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`endif
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VX_dcr_bus_if.slave dcr_bus_if,
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VX_mem_bus_if.master dcache_bus_if [DCACHE_NUM_REQS],
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VX_mem_bus_if.master icache_bus_if,
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`ifdef GBAR_ENABLE
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VX_gbar_bus_if.master gbar_bus_if,
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`endif
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// simulation helper signals
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output wire sim_ebreak,
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output wire [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value,
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// Status
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output wire busy
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);
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VX_schedule_if schedule_if();
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VX_fetch_if fetch_if();
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VX_decode_if decode_if();
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VX_sched_csr_if sched_csr_if();
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VX_decode_sched_if decode_sched_if();
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VX_commit_sched_if commit_sched_if();
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VX_commit_csr_if commit_csr_if();
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VX_branch_ctl_if branch_ctl_if[`NUM_ALU_BLOCKS]();
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VX_warp_ctl_if warp_ctl_if();
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VX_dispatch_if alu_dispatch_if[`ISSUE_WIDTH]();
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VX_commit_if alu_commit_if[`ISSUE_WIDTH]();
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VX_dispatch_if lsu_dispatch_if[`ISSUE_WIDTH]();
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VX_commit_if lsu_commit_if[`ISSUE_WIDTH]();
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`ifdef EXT_F_ENABLE
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VX_dispatch_if fpu_dispatch_if[`ISSUE_WIDTH]();
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VX_commit_if fpu_commit_if[`ISSUE_WIDTH]();
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`endif
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VX_dispatch_if sfu_dispatch_if[`ISSUE_WIDTH]();
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VX_commit_if sfu_commit_if[`ISSUE_WIDTH]();
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VX_writeback_if writeback_if[`ISSUE_WIDTH]();
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VX_mem_bus_if #(
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.DATA_SIZE (DCACHE_WORD_SIZE),
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.TAG_WIDTH (DCACHE_TAG_WIDTH)
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) dcache_bus_tmp_if[DCACHE_NUM_REQS]();
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`ifdef PERF_ENABLE
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VX_pipeline_perf_if pipeline_perf_if();
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VX_mem_perf_if mem_perf_tmp_if();
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assign mem_perf_tmp_if.icache = mem_perf_if.icache;
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assign mem_perf_tmp_if.dcache = mem_perf_if.dcache;
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assign mem_perf_tmp_if.l2cache = mem_perf_if.l2cache;
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assign mem_perf_tmp_if.l3cache = mem_perf_if.l3cache;
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`ifdef SM_ENABLE
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cache_perf_t smem_perf;
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assign mem_perf_tmp_if.smem = smem_perf;
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`else
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assign mem_perf_tmp_if.smem = '0;
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`endif
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assign mem_perf_tmp_if.mem = mem_perf_if.mem;
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`endif
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`RESET_RELAY (dcr_data_reset, reset);
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`RESET_RELAY (schedule_reset, reset);
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`RESET_RELAY (fetch_reset, reset);
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`RESET_RELAY (decode_reset, reset);
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`RESET_RELAY (issue_reset, reset);
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`RESET_RELAY (execute_reset, reset);
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`RESET_RELAY (commit_reset, reset);
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base_dcrs_t base_dcrs;
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VX_dcr_data dcr_data (
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.clk (clk),
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.reset (dcr_data_reset),
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.dcr_bus_if (dcr_bus_if),
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.base_dcrs (base_dcrs)
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);
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`SCOPE_IO_SWITCH (3)
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VX_schedule #(
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.CORE_ID (CORE_ID)
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) schedule (
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.clk (clk),
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.reset (schedule_reset),
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.base_dcrs (base_dcrs),
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.warp_ctl_if (warp_ctl_if),
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.branch_ctl_if (branch_ctl_if),
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.decode_sched_if(decode_sched_if),
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.commit_sched_if(commit_sched_if),
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.schedule_if (schedule_if),
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`ifdef GBAR_ENABLE
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.gbar_bus_if (gbar_bus_if),
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`endif
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.sched_csr_if (sched_csr_if),
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.busy (busy)
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);
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VX_fetch #(
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.CORE_ID (CORE_ID)
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) fetch (
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`SCOPE_IO_BIND (0)
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.clk (clk),
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.reset (fetch_reset),
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.icache_bus_if (icache_bus_if),
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.schedule_if (schedule_if),
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.fetch_if (fetch_if)
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);
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VX_decode #(
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.CORE_ID (CORE_ID)
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) decode (
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.clk (clk),
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.reset (decode_reset),
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.fetch_if (fetch_if),
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.decode_if (decode_if),
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.decode_sched_if(decode_sched_if)
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);
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VX_issue #(
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.CORE_ID (CORE_ID)
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) issue (
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`SCOPE_IO_BIND (1)
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.clk (clk),
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.reset (issue_reset),
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`ifdef PERF_ENABLE
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.perf_issue_if (pipeline_perf_if.issue),
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`endif
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.decode_if (decode_if),
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.writeback_if (writeback_if),
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.alu_dispatch_if(alu_dispatch_if),
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.lsu_dispatch_if(lsu_dispatch_if),
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`ifdef EXT_F_ENABLE
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.fpu_dispatch_if(fpu_dispatch_if),
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`endif
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.sfu_dispatch_if(sfu_dispatch_if)
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);
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VX_execute #(
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.CORE_ID (CORE_ID)
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) execute (
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`SCOPE_IO_BIND (2)
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.clk (clk),
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.reset (execute_reset),
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.base_dcrs (base_dcrs),
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`ifdef PERF_ENABLE
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.mem_perf_if (mem_perf_tmp_if),
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.pipeline_perf_if(pipeline_perf_if),
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`endif
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.dcache_bus_if (dcache_bus_tmp_if),
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`ifdef EXT_F_ENABLE
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.fpu_dispatch_if(fpu_dispatch_if),
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.fpu_commit_if (fpu_commit_if),
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`endif
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.commit_csr_if (commit_csr_if),
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.sched_csr_if (sched_csr_if),
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.alu_dispatch_if(alu_dispatch_if),
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.lsu_dispatch_if(lsu_dispatch_if),
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.sfu_dispatch_if(sfu_dispatch_if),
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.warp_ctl_if (warp_ctl_if),
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.branch_ctl_if (branch_ctl_if),
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.alu_commit_if (alu_commit_if),
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.lsu_commit_if (lsu_commit_if),
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.sfu_commit_if (sfu_commit_if),
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.sim_ebreak (sim_ebreak)
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);
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VX_commit #(
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.CORE_ID (CORE_ID)
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) commit (
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.clk (clk),
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.reset (commit_reset),
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.alu_commit_if (alu_commit_if),
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.lsu_commit_if (lsu_commit_if),
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`ifdef EXT_F_ENABLE
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.fpu_commit_if (fpu_commit_if),
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`endif
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.sfu_commit_if (sfu_commit_if),
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.writeback_if (writeback_if),
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.commit_csr_if (commit_csr_if),
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.commit_sched_if(commit_sched_if),
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.sim_wb_value (sim_wb_value)
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);
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`ifdef SM_ENABLE
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VX_smem_unit #(
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.CORE_ID (CORE_ID)
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) smem_unit (
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.clk (clk),
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.reset (reset),
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`ifdef PERF_ENABLE
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.cache_perf (smem_perf),
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`endif
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.dcache_bus_in_if (dcache_bus_tmp_if),
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.dcache_bus_out_if (dcache_bus_if)
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);
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`else
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for (genvar i = 0; i < DCACHE_NUM_REQS; ++i) begin
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`ASSIGN_VX_MEM_BUS_IF (dcache_bus_if[i], dcache_bus_tmp_if[i]);
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end
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`endif
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`ifdef PERF_ENABLE
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wire [`CLOG2(DCACHE_NUM_REQS+1)-1:0] perf_dcache_rd_req_per_cycle;
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wire [`CLOG2(DCACHE_NUM_REQS+1)-1:0] perf_dcache_wr_req_per_cycle;
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wire [`CLOG2(DCACHE_NUM_REQS+1)-1:0] perf_dcache_rsp_per_cycle;
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wire perf_icache_pending_read_cycle;
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wire [`CLOG2(DCACHE_NUM_REQS+1)+1-1:0] perf_dcache_pending_read_cycle;
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reg [`PERF_CTR_BITS-1:0] perf_icache_pending_reads;
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reg [`PERF_CTR_BITS-1:0] perf_dcache_pending_reads;
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reg [`PERF_CTR_BITS-1:0] perf_ifetches;
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reg [`PERF_CTR_BITS-1:0] perf_loads;
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reg [`PERF_CTR_BITS-1:0] perf_stores;
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wire perf_icache_req_fire = icache_bus_if.req_valid & icache_bus_if.req_ready;
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wire perf_icache_rsp_fire = icache_bus_if.rsp_valid & icache_bus_if.rsp_ready;
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wire [DCACHE_NUM_REQS-1:0] perf_dcache_rd_req_fire, perf_dcache_wr_req_fire, perf_dcache_rsp_fire;
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for (genvar i = 0; i < DCACHE_NUM_REQS; ++i) begin
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assign perf_dcache_rd_req_fire[i] = dcache_bus_if[i].req_valid && ~dcache_bus_if[i].req_data.rw && dcache_bus_if[i].req_ready;
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assign perf_dcache_wr_req_fire[i] = dcache_bus_if[i].req_valid && dcache_bus_if[i].req_data.rw && dcache_bus_if[i].req_ready;
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assign perf_dcache_rsp_fire[i] = dcache_bus_if[i].rsp_valid && dcache_bus_if[i].rsp_ready;
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end
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`POP_COUNT(perf_dcache_rd_req_per_cycle, perf_dcache_rd_req_fire);
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`POP_COUNT(perf_dcache_wr_req_per_cycle, perf_dcache_wr_req_fire);
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`POP_COUNT(perf_dcache_rsp_per_cycle, perf_dcache_rsp_fire);
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assign perf_icache_pending_read_cycle = perf_icache_req_fire - perf_icache_rsp_fire;
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assign perf_dcache_pending_read_cycle = perf_dcache_rd_req_per_cycle - perf_dcache_rsp_per_cycle;
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always @(posedge clk) begin
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if (reset) begin
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perf_icache_pending_reads <= '0;
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perf_dcache_pending_reads <= '0;
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end else begin
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perf_icache_pending_reads <= $signed(perf_icache_pending_reads) + `PERF_CTR_BITS'($signed(perf_icache_pending_read_cycle));
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perf_dcache_pending_reads <= $signed(perf_dcache_pending_reads) + `PERF_CTR_BITS'($signed(perf_dcache_pending_read_cycle));
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end
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end
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reg [`PERF_CTR_BITS-1:0] perf_icache_lat;
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reg [`PERF_CTR_BITS-1:0] perf_dcache_lat;
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always @(posedge clk) begin
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if (reset) begin
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perf_ifetches <= '0;
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perf_loads <= '0;
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perf_stores <= '0;
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perf_icache_lat <= '0;
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perf_dcache_lat <= '0;
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end else begin
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perf_ifetches <= perf_ifetches + `PERF_CTR_BITS'(perf_icache_req_fire);
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perf_loads <= perf_loads + `PERF_CTR_BITS'(perf_dcache_rd_req_per_cycle);
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perf_stores <= perf_stores + `PERF_CTR_BITS'(perf_dcache_wr_req_per_cycle);
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perf_icache_lat <= perf_icache_lat + perf_icache_pending_reads;
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perf_dcache_lat <= perf_dcache_lat + perf_dcache_pending_reads;
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end
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end
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assign pipeline_perf_if.ifetches = perf_ifetches;
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assign pipeline_perf_if.loads = perf_loads;
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assign pipeline_perf_if.stores = perf_stores;
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assign pipeline_perf_if.load_latency = perf_dcache_lat;
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assign pipeline_perf_if.ifetch_latency = perf_icache_lat;
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assign pipeline_perf_if.load_latency = perf_dcache_lat;
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`endif
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endmodule
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