33 lines
642 B
Systemverilog
33 lines
642 B
Systemverilog
`ifndef VX_FPU_TO_CSR_IF
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`define VX_FPU_TO_CSR_IF
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`include "VX_define.vh"
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interface VX_fpu_to_csr_if ();
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wire write_enable;
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wire [`NW_BITS-1:0] write_wid;
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fpu_types::fflags_t write_fflags;
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wire [`NW_BITS-1:0] read_wid;
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wire [`INST_FRM_BITS-1:0] read_frm;
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modport master (
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output write_enable,
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output write_wid,
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output write_fflags,
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output read_wid,
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input read_frm
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);
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modport slave (
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input write_enable,
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input write_wid,
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input write_fflags,
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input read_wid,
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output read_frm
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);
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endinterface
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`endif |