98 lines
3.8 KiB
Verilog
98 lines
3.8 KiB
Verilog
`include "VX_define.vh"
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module VX_inst_multiplex (
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// Inputs
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VX_frE_to_bckE_req_inter vx_bckE_req,
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VX_gpr_data_inter vx_gpr_data,
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// Outputs
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VX_exec_unit_req_inter vx_exec_unit_req,
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VX_lsu_req_inter vx_lsu_req,
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VX_gpu_inst_req_inter vx_gpu_inst_req,
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VX_csr_req_inter vx_csr_req
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);
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wire[`NUM_THREADS-1:0] is_mem_mask;
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wire[`NUM_THREADS-1:0] is_gpu_mask;
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wire[`NUM_THREADS-1:0] is_csr_mask;
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wire is_mem = (vx_bckE_req.mem_write != `NO_MEM_WRITE) || (vx_bckE_req.mem_read != `NO_MEM_READ);
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wire is_gpu = (vx_bckE_req.is_wspawn || vx_bckE_req.is_tmc || vx_bckE_req.is_barrier || vx_bckE_req.is_split);
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wire is_csr = vx_bckE_req.is_csr;
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// wire is_gpu = 0;
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genvar currT;
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generate
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for (currT = 0; currT < `NUM_THREADS; currT = currT + 1) begin : mask_init
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assign is_mem_mask[currT] = is_mem;
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assign is_gpu_mask[currT] = is_gpu;
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assign is_csr_mask[currT] = is_csr;
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end
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endgenerate
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// LSU Unit
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assign vx_lsu_req.valid = vx_bckE_req.valid & is_mem_mask;
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assign vx_lsu_req.warp_num = vx_bckE_req.warp_num;
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assign vx_lsu_req.base_address = vx_gpr_data.a_reg_data;
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assign vx_lsu_req.store_data = vx_gpr_data.b_reg_data;
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assign vx_lsu_req.offset = vx_bckE_req.itype_immed;
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assign vx_lsu_req.mem_read = vx_bckE_req.mem_read;
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assign vx_lsu_req.mem_write = vx_bckE_req.mem_write;
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assign vx_lsu_req.rd = vx_bckE_req.rd;
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assign vx_lsu_req.wb = vx_bckE_req.wb;
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assign vx_lsu_req.lsu_pc = vx_bckE_req.curr_PC;
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// Execute Unit
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assign vx_exec_unit_req.valid = vx_bckE_req.valid & (~is_mem_mask & ~is_gpu_mask & ~is_csr_mask);
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assign vx_exec_unit_req.warp_num = vx_bckE_req.warp_num;
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assign vx_exec_unit_req.curr_PC = vx_bckE_req.curr_PC;
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assign vx_exec_unit_req.PC_next = vx_bckE_req.PC_next;
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assign vx_exec_unit_req.rd = vx_bckE_req.rd;
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assign vx_exec_unit_req.wb = vx_bckE_req.wb;
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assign vx_exec_unit_req.a_reg_data = vx_gpr_data.a_reg_data;
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assign vx_exec_unit_req.b_reg_data = vx_gpr_data.b_reg_data;
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assign vx_exec_unit_req.alu_op = vx_bckE_req.alu_op;
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assign vx_exec_unit_req.rs1 = vx_bckE_req.rs1;
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assign vx_exec_unit_req.rs2 = vx_bckE_req.rs2;
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assign vx_exec_unit_req.rs2_src = vx_bckE_req.rs2_src;
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assign vx_exec_unit_req.itype_immed = vx_bckE_req.itype_immed;
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assign vx_exec_unit_req.upper_immed = vx_bckE_req.upper_immed;
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assign vx_exec_unit_req.branch_type = vx_bckE_req.branch_type;
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assign vx_exec_unit_req.jalQual = vx_bckE_req.jalQual;
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assign vx_exec_unit_req.jal = vx_bckE_req.jal;
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assign vx_exec_unit_req.jal_offset = vx_bckE_req.jal_offset;
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assign vx_exec_unit_req.ebreak = vx_bckE_req.ebreak;
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// GPR Req
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assign vx_gpu_inst_req.valid = vx_bckE_req.valid & is_gpu_mask;
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assign vx_gpu_inst_req.warp_num = vx_bckE_req.warp_num;
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assign vx_gpu_inst_req.is_wspawn = vx_bckE_req.is_wspawn;
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assign vx_gpu_inst_req.is_tmc = vx_bckE_req.is_tmc;
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assign vx_gpu_inst_req.is_split = vx_bckE_req.is_split;
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assign vx_gpu_inst_req.is_barrier = vx_bckE_req.is_barrier;
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assign vx_gpu_inst_req.a_reg_data = vx_gpr_data.a_reg_data;
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assign vx_gpu_inst_req.rd2 = vx_gpr_data.b_reg_data[0];
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assign vx_gpu_inst_req.pc_next = vx_bckE_req.PC_next;
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// CSR Req
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assign vx_csr_req.valid = vx_bckE_req.valid & is_csr_mask;
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assign vx_csr_req.warp_num = vx_bckE_req.warp_num;
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assign vx_csr_req.rd = vx_bckE_req.rd;
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assign vx_csr_req.wb = vx_bckE_req.wb;
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assign vx_csr_req.alu_op = vx_bckE_req.alu_op;
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assign vx_csr_req.is_csr = vx_bckE_req.is_csr;
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assign vx_csr_req.csr_address = vx_bckE_req.csr_address;
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assign vx_csr_req.csr_immed = vx_bckE_req.csr_immed;
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assign vx_csr_req.csr_mask = vx_bckE_req.csr_mask;
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endmodule
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