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9a077b97f3c40a4fba33495dd3c391a207387e49
kernels/hw/rtl/cache
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Blaise Tine 4d55118545 cache pipeline optimization - moved tag access to stage0
2021-01-03 23:10:41 -05:00
..
VX_bank.v
cache pipeline optimization - moved tag access to stage0
2021-01-03 23:10:41 -05:00
VX_cache_config.vh
scratchpad optimization for stack access using custom bank offset aligned to stack size
2021-01-02 16:00:00 -05:00
VX_cache_core_req_bank_sel.v
scratchpad optimization for stack access using custom bank offset aligned to stack size
2021-01-02 16:00:00 -05:00
VX_cache_core_rsp_merge.v
critical path optimization - fpga fmax @4c = ~212 mhz
2020-12-26 03:28:32 -08:00
VX_cache.v
cache fill response address is the mshr's top address, no need to store it
2021-01-03 00:57:24 -05:00
VX_data_access.v
cache pipeline optimization - moved tag access to stage0
2021-01-03 23:10:41 -05:00
VX_data_store.v
scratchpad optimization for stack access using custom bank offset aligned to stack size
2021-01-02 16:00:00 -05:00
VX_miss_resrv.v
using single-port block ram for cache tags, restoring core reset signal
2021-01-02 19:53:41 -08:00
VX_tag_access.v
cache pipeline optimization - moved tag access to stage0
2021-01-03 23:10:41 -05:00
VX_tag_store.v
cache pipeline optimization - moved tag access to stage0
2021-01-03 23:10:41 -05:00
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