78 lines
2.2 KiB
Verilog
78 lines
2.2 KiB
Verilog
`include "VX_platform.vh"
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module VX_gpr_bypass #(
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parameter DATAW = 1,
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parameter PASSTHRU = 0
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) (
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input wire clk,
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input wire reset,
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input wire push,
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input wire pop,
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input wire [DATAW-1:0] data_in,
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output wire [DATAW-1:0] data_out
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);
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if (PASSTHRU) begin
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reg delayed_push;
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always @(posedge clk) begin
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if (reset) begin
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delayed_push <= 0;
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end else begin
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delayed_push <= push;
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assert(!delayed_push || pop);
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end
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end
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assign data_out = data_in;
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end else begin
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reg [DATAW-1:0] buffer, buffer2;
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reg use_buffer, use_buffer2;
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reg delayed_push;
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always @(posedge clk) begin
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if (reset) begin
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delayed_push <= 0;
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use_buffer <= 0;
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use_buffer2 <= 0;
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end else begin
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delayed_push <= push;
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assert(!use_buffer2 || use_buffer);
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if (pop) begin
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use_buffer <= use_buffer2;
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use_buffer2 <= 0;
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end
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if (delayed_push) begin
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if (use_buffer) begin
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assert(!use_buffer2); // full!
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use_buffer <= 1;
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if (!pop) begin
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use_buffer2 <= 1;
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end
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end else if (!pop) begin
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use_buffer <= 1;
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end
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end
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end
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if (pop) begin
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buffer <= buffer2;
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end
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if (delayed_push) begin
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if (use_buffer) begin
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if (pop) begin
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buffer <= data_in;
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end else begin
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buffer2 <= data_in;
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end
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end else if (!pop) begin
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buffer <= data_in;
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end
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end
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end
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assign data_out = use_buffer ? buffer : data_in;
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end
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endmodule |