d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
110 lines
3.5 KiB
Systemverilog
110 lines
3.5 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_divider #(
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parameter N_WIDTH = 1,
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parameter D_WIDTH = 1,
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parameter Q_WIDTH = 1,
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parameter R_WIDTH = 1,
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parameter N_SIGNED = 0,
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parameter D_SIGNED = 0,
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parameter LATENCY = 0
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) (
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input wire clk,
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input wire enable,
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input wire [N_WIDTH-1:0] numer,
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input wire [D_WIDTH-1:0] denom,
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output wire [Q_WIDTH-1:0] quotient,
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output wire [R_WIDTH-1:0] remainder
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);
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`ifdef QUARTUS
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wire [N_WIDTH-1:0] quotient_unqual;
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wire [D_WIDTH-1:0] remainder_unqual;
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lpm_divide divide (
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.clock (clk),
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.clken (enable),
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.numer (numer),
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.denom (denom),
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.quotient (quotient_unqual),
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.remain (remainder_unqual)
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);
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defparam
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divide.lpm_type = "LPM_DIVIDE",
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divide.lpm_widthn = N_WIDTH,
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divide.lpm_widthd = D_WIDTH,
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divide.lpm_nrepresentation = N_SIGNED ? "SIGNED" : "UNSIGNED",
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divide.lpm_drepresentation = D_SIGNED ? "SIGNED" : "UNSIGNED",
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divide.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE",
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divide.lpm_pipeline = LATENCY;
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assign quotient = quotient_unqual [Q_WIDTH-1:0];
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assign remainder = remainder_unqual [R_WIDTH-1:0];
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`else
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reg [N_WIDTH-1:0] quotient_unqual;
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reg [D_WIDTH-1:0] remainder_unqual;
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always @(*) begin
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begin
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if (N_SIGNED && D_SIGNED) begin
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quotient_unqual = $signed(numer) / $signed(denom);
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remainder_unqual = $signed(numer) % $signed(denom);
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end
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else if (N_SIGNED && !D_SIGNED) begin
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quotient_unqual = $signed(numer) / denom;
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remainder_unqual = $signed(numer) % denom;
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end
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else if (!N_SIGNED && D_SIGNED) begin
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quotient_unqual = numer / $signed(denom);
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remainder_unqual = numer % $signed(denom);
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end
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else begin
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quotient_unqual = numer / denom;
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remainder_unqual = numer % denom;
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end
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end
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end
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if (LATENCY == 0) begin
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assign quotient = quotient_unqual [Q_WIDTH-1:0];
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assign remainder = remainder_unqual [R_WIDTH-1:0];
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end else begin
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reg [N_WIDTH-1:0] quotient_pipe [LATENCY-1:0];
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reg [D_WIDTH-1:0] remainder_pipe [LATENCY-1:0];
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for (genvar i = 0; i < LATENCY; ++i) begin
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always @(posedge clk) begin
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if (enable) begin
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quotient_pipe[i] <= (0 == i) ? quotient_unqual : quotient_pipe[i-1];
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remainder_pipe[i] <= (0 == i) ? remainder_unqual : remainder_pipe[i-1];
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end
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end
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end
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assign quotient = quotient_pipe[LATENCY-1][Q_WIDTH-1:0];
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assign remainder = remainder_pipe[LATENCY-1][R_WIDTH-1:0];
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end
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`endif
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endmodule
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`TRACING_ON
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