d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
77 lines
2.6 KiB
Systemverilog
77 lines
2.6 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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module VX_split_join import VX_gpu_pkg::*; #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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input wire valid,
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input wire [`NW_WIDTH-1:0] wid,
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input split_t split,
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input join_t sjoin,
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output wire join_valid,
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output wire join_is_dvg,
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output wire join_is_else,
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output wire [`NW_WIDTH-1:0] join_wid,
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output wire [`NUM_THREADS-1:0] join_tmask,
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output wire [`XLEN-1:0] join_pc
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);
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`UNUSED_PARAM (CORE_ID)
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wire [(`XLEN+`NUM_THREADS)-1:0] ipdom_data [`NUM_WARPS-1:0];
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wire ipdom_set [`NUM_WARPS-1:0];
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wire [(`XLEN+`NUM_THREADS)-1:0] ipdom_q0 = {split.then_tmask | split.else_tmask, `XLEN'(0)};
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wire [(`XLEN+`NUM_THREADS)-1:0] ipdom_q1 = {split.else_tmask, split.next_pc};
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wire ipdom_push = valid && split.valid && split.is_dvg;
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wire ipdom_pop = valid && sjoin.valid && sjoin.is_dvg;
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for (genvar i = 0; i < `NUM_WARPS; ++i) begin
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`RESET_RELAY (ipdom_reset, reset);
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VX_ipdom_stack #(
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.WIDTH (`XLEN+`NUM_THREADS),
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.DEPTH (`UP(`NUM_THREADS-1))
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) ipdom_stack (
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.clk (clk),
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.reset (ipdom_reset),
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.push (ipdom_push && (i == wid)),
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.pop (ipdom_pop && (i == wid)),
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.q0 (ipdom_q0),
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.q1 (ipdom_q1),
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.d (ipdom_data[i]),
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.d_set (ipdom_set[i]),
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`UNUSED_PIN (empty),
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`UNUSED_PIN (full)
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);
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end
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VX_pipe_register #(
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.DATAW (1 + 1 + `NW_WIDTH + 1 + `XLEN + `NUM_THREADS),
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.DEPTH (1),
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.RESETW (1)
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) pipe_reg (
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.clk (clk),
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.reset (reset),
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.enable (1'b1),
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.data_in ({valid && sjoin.valid, sjoin.is_dvg, ipdom_set[wid], wid, ipdom_data[wid]}),
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.data_out ({join_valid, join_is_dvg, join_is_else, join_wid, join_tmask, join_pc})
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);
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endmodule
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