146 lines
5.3 KiB
Verilog
146 lines
5.3 KiB
Verilog
`include "VX_define.vh"
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module VX_mul_unit #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// Inputs
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VX_mul_req_if mul_req_if,
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// Outputs
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VX_commit_if mul_commit_if
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);
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wire [`MUL_BITS-1:0] alu_op = mul_req_if.op_type;
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wire is_div_op = `IS_DIV_OP(alu_op);
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wire [`NUM_THREADS-1:0][31:0] alu_in1 = mul_req_if.rs1_data;
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wire [`NUM_THREADS-1:0][31:0] alu_in2 = mul_req_if.rs2_data;
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wire ready_out;
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///////////////////////////////////////////////////////////////////////////
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wire [`NUM_THREADS-1:0][31:0] mul_result;
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wire [`NW_BITS-1:0] mul_wid_out;
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wire [`NUM_THREADS-1:0] mul_tmask_out;
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wire [31:0] mul_PC_out;
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wire [`NR_BITS-1:0] mul_rd_out;
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wire mul_wb_out;
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wire mul_valid_out;
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wire mul_valid_in = mul_req_if.valid && !is_div_op;
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wire mul_ready_in = ready_out || ~mul_valid_out;
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wire is_mulh_in = (alu_op != `MUL_MUL);
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wire is_mulh_out;
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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wire [32:0] mul_in1 = {(alu_op != `MUL_MULHU) & alu_in1[i][31], alu_in1[i]};
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wire [32:0] mul_in2 = {(alu_op != `MUL_MULHU && alu_op != `MUL_MULHSU) & alu_in2[i][31], alu_in2[i]};
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`IGNORE_WARNINGS_BEGIN
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wire [65:0] mul_result_tmp;
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`IGNORE_WARNINGS_END
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VX_multiplier #(
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.WIDTHA (33),
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.WIDTHB (33),
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.WIDTHP (66),
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.SIGNED (1),
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.LATENCY (`LATENCY_IMUL)
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) multiplier (
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.clk (clk),
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.enable (mul_ready_in),
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.dataa (mul_in1),
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.datab (mul_in2),
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.result (mul_result_tmp)
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);
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assign mul_result[i] = is_mulh_out ? mul_result_tmp[63:32] : mul_result_tmp[31:0];
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end
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VX_shift_register #(
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.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + 1),
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.DEPTH (`LATENCY_IMUL),
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.RESETW (1)
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) mul_shift_reg (
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.clk(clk),
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.reset (reset),
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.enable (mul_ready_in),
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.data_in ({mul_valid_in, mul_req_if.wid, mul_req_if.tmask, mul_req_if.PC, mul_req_if.rd, mul_req_if.wb, is_mulh_in}),
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.data_out ({mul_valid_out, mul_wid_out, mul_tmask_out, mul_PC_out, mul_rd_out, mul_wb_out, is_mulh_out})
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);
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///////////////////////////////////////////////////////////////////////////
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wire [`NUM_THREADS-1:0][31:0] div_result_tmp, rem_result_tmp;
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wire [`NW_BITS-1:0] div_wid_out;
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wire [`NUM_THREADS-1:0] div_tmask_out;
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wire [31:0] div_PC_out;
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wire [`NR_BITS-1:0] div_rd_out;
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wire div_wb_out;
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wire is_rem_op_in = (alu_op == `MUL_REM) || (alu_op == `MUL_REMU);
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wire is_signed_div = (alu_op == `MUL_DIV) || (alu_op == `MUL_REM);
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wire div_valid_in = mul_req_if.valid && is_div_op;
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wire div_ready_out = ready_out && ~mul_valid_out; // arbitration prioritizes MUL
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wire div_ready_in;
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wire div_valid_out;
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wire is_rem_op_out;
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VX_serial_div #(
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.WIDTHN (32),
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.WIDTHD (32),
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.WIDTHQ (32),
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.WIDTHR (32),
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.LANES (`NUM_THREADS),
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.TAGW (`NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + 1)
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) divide (
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.clk (clk),
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.reset (reset),
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.valid_in (div_valid_in),
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.ready_in (div_ready_in),
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.signed_mode(is_signed_div),
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.tag_in ({mul_req_if.wid, mul_req_if.tmask, mul_req_if.PC, mul_req_if.rd, mul_req_if.wb, is_rem_op_in}),
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.numer (alu_in1),
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.denom (alu_in2),
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.quotient (div_result_tmp),
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.remainder (rem_result_tmp),
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.ready_out (div_ready_out),
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.valid_out (div_valid_out),
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.tag_out ({div_wid_out, div_tmask_out, div_PC_out, div_rd_out, div_wb_out, is_rem_op_out})
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);
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wire [`NUM_THREADS-1:0][31:0] div_result = is_rem_op_out ? rem_result_tmp : div_result_tmp;
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///////////////////////////////////////////////////////////////////////////
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wire stall_out = ~mul_commit_if.ready && mul_commit_if.valid;
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assign ready_out = ~stall_out;
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wire rsp_valid = mul_valid_out || div_valid_out;
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wire [`NW_BITS-1:0] rsp_wid = mul_valid_out ? mul_wid_out : div_wid_out;
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wire [`NUM_THREADS-1:0] rsp_tmask = mul_valid_out ? mul_tmask_out : div_tmask_out;
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wire [31:0] rsp_PC = mul_valid_out ? mul_PC_out : div_PC_out;
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wire [`NR_BITS-1:0] rsp_rd = mul_valid_out ? mul_rd_out : div_rd_out;
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wire rsp_wb = mul_valid_out ? mul_wb_out : div_wb_out;
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wire [`NUM_THREADS-1:0][31:0] rsp_data = mul_valid_out ? mul_result : div_result;
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VX_pipe_register #(
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.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32)),
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.RESETW (1)
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) pipe_reg (
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.clk (clk),
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.reset (reset),
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.enable (!stall_out),
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.data_in ({rsp_valid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, rsp_data}),
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.data_out ({mul_commit_if.valid, mul_commit_if.wid, mul_commit_if.tmask, mul_commit_if.PC, mul_commit_if.rd, mul_commit_if.wb, mul_commit_if.data})
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);
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assign mul_commit_if.eop = 1'b1;
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// can accept new request?
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assign mul_req_if.ready = is_div_op ? div_ready_in : mul_ready_in;
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endmodule |