22 lines
283 B
Verilog
22 lines
283 B
Verilog
module VX_countones
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#(
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parameter N = 10
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)
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(
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input wire[N-1:0] valids,
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output reg[$clog2(N):0] count
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);
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integer i;
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always @(*) begin
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count = 0;
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for (i = N-1; i >= 0; i = i - 1) begin
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if (valids[i]) begin
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count = count + 1;
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end
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end
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end
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endmodule |