89 lines
2.8 KiB
Verilog
89 lines
2.8 KiB
Verilog
`include "VX_define.vh"
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module VX_lsu (
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input wire clk,
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input wire reset,
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input wire no_slot_mem,
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VX_lsu_req_inter vx_lsu_req,
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// Write back to GPR
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VX_inst_mem_wb_inter vx_mem_wb,
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VX_gpu_dcache_rsp_inter vx_dcache_rsp,
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VX_gpu_dcache_req_inter vx_dcache_req,
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output wire out_delay
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);
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// Generate Addresses
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wire[`NUM_THREADS-1:0][31:0] address;
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VX_lsu_addr_gen VX_lsu_addr_gen (
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.base_address (vx_lsu_req.base_address),
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.offset (vx_lsu_req.offset),
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.address (address)
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);
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wire[`NUM_THREADS-1:0][31:0] use_address;
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wire[`NUM_THREADS-1:0][31:0] use_store_data;
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wire[`NUM_THREADS-1:0] use_valid;
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wire[2:0] use_mem_read;
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wire[2:0] use_mem_write;
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wire[4:0] use_rd;
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wire[`NW_BITS-1:0] use_warp_num;
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wire[1:0] use_wb;
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wire[31:0] use_pc;
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wire zero = 0;
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VX_generic_register #(
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.N(45 + `NW_BITS-1 + 1 + `NUM_THREADS*65)
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) lsu_buffer(
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.clk (clk),
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.reset(reset),
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.stall(out_delay),
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.flush(zero),
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.in ({address , vx_lsu_req.store_data, vx_lsu_req.valid, vx_lsu_req.mem_read, vx_lsu_req.mem_write, vx_lsu_req.rd, vx_lsu_req.warp_num, vx_lsu_req.wb, vx_lsu_req.lsu_pc}),
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.out ({use_address, use_store_data , use_valid , use_mem_read , use_mem_write , use_rd , use_warp_num , use_wb , use_pc })
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);
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// Core Request
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assign vx_dcache_req.core_req_valid = use_valid;
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assign vx_dcache_req.core_req_addr = use_address;
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assign vx_dcache_req.core_req_writedata = use_store_data;
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assign vx_dcache_req.core_req_mem_read = {`NUM_THREADS{use_mem_read}};
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assign vx_dcache_req.core_req_mem_write = {`NUM_THREADS{use_mem_write}};
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assign vx_dcache_req.core_req_rd = use_rd;
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assign vx_dcache_req.core_req_wb = {`NUM_THREADS{use_wb}};
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assign vx_dcache_req.core_req_warp_num = use_warp_num;
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assign vx_dcache_req.core_req_pc = use_pc;
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// Core can't accept response
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assign vx_dcache_req.core_no_wb_slot = no_slot_mem;
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// Cache can't accept request
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assign out_delay = vx_dcache_rsp.delay_req;
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// Core Response
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assign vx_mem_wb.rd = vx_dcache_rsp.core_wb_req_rd;
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assign vx_mem_wb.wb = vx_dcache_rsp.core_wb_req_wb;
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assign vx_mem_wb.wb_valid = vx_dcache_rsp.core_wb_valid;
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assign vx_mem_wb.wb_warp_num = vx_dcache_rsp.core_wb_warp_num;
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assign vx_mem_wb.loaded_data = vx_dcache_rsp.core_wb_readdata;
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wire[(`LOG2UP(`NUM_THREADS))-1:0] use_pc_index;
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`DEBUG_BEGIN
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wire found;
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`DEBUG_END
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VX_generic_priority_encoder #(.N(`NUM_THREADS)) pick_first_pc(
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.valids(vx_dcache_rsp.core_wb_valid),
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.index (use_pc_index),
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.found (found)
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);
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assign vx_mem_wb.mem_wb_pc = vx_dcache_rsp.core_wb_pc[use_pc_index];
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endmodule // Memory
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