213 lines
7.9 KiB
Verilog
213 lines
7.9 KiB
Verilog
`include "VX_cache_config.v"
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module VX_bank (
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input wire clk,
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input wire reset,
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// Input Core Request
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input wire delay_req,
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input wire [`NUMBER_REQUESTS-1:0] bank_valids,
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input wire [`NUMBER_REQUESTS-1:0][31:0] bank_addr,
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input wire [`NUMBER_REQUESTS-1:0][31:0] bank_writedata,
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input wire [4:0] bank_rd,
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input wire [1:0] bank_wb,
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input wire [`NW_M1:0] bank_warp_num,
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input wire [2:0] bank_mem_read,
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input wire [2:0] bank_mem_write,
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output wire reqq_full,
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// Output Core WB
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input wire bank_wb_pop,
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output wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] bank_wb_tid,
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output wire [4:0] bank_wb_rd,
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output wire [1:0] bank_wb_wb,
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output wire [`NW_M1:0] bank_wb_warp_num,
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output wire [31:0] bank_wb_data,
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// Dram Fill Requests
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output wire dram_fill_req,
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output wire[31:0] dram_fill_req_addr,
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input wire dram_fill_req_queue_full,
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// Dram Fill Response
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input wire dram_fill_rsp,
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input wire [31:0] dram_fill_addr,
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input wire[`BANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data,
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output wire dram_fill_accept,
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// Dram WB Requests
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input wire dram_wb_queue_pop,
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output wire dram_wb_req,
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output wire[31:0] dram_wb_req_addr,
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output wire[`BANK_LINE_SIZE_RNG][31:0] dram_wb_req_data
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);
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wire dfpq_pop; // Use this
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wire dfpq_empty;
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wire dfpq_full;
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wire[31:0] dfpq_addr_st0;
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wire[`BANK_LINE_SIZE_RNG][31:0] dfpq_filldata_st0;
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assign dram_fill_accept = !dfpq_full;
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VX_generic_queue #(.DATAW(32+(`BANK_LINE_SIZE_WORDS*32)), .SIZE(`DFPQ_SIZE)) dfp_queue(
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.clk (clk),
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.reset (reset),
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.push (dram_fill_rsp),
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.in_data ({dram_fill_addr, dram_fill_rsp_data}),
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.pop (dfpq_pop),
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.out_data({dfpq_addr_st0, dfpq_filldata_st0}),
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.empty (dfpq_empty),
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.full (dfpq_full)
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);
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wire reqq_pop; // Use this
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wire reqq_push;
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wire reqq_empty;
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wire reqq_req_st0;
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wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] reqq_req_tid_st0;
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wire [31:0] reqq_req_addr_st0;
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wire [31:0] reqq_req_writeword_st0;
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wire [4:0] reqq_req_rd_st0;
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wire [1:0] reqq_req_wb_st0;
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wire [`NW_M1:0] reqq_req_warp_num_st0;
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wire [2:0] reqq_req_mem_read_st0;
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wire [2:0] reqq_req_mem_write_st0;
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assign reqq_push = !delay_req && (|bank_valids);
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VX_cache_req_queue mrvq_queue(
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.clk (clk),
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.reset (reset),
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// Enqueue
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.reqq_push (reqq_push),
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.bank_valids (bank_valids),
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.bank_addr (bank_addr),
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.bank_writedata (bank_writedata),
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.bank_rd (bank_rd),
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.bank_wb (bank_wb),
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.bank_warp_num (bank_warp_num),
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.bank_mem_read (bank_mem_read),
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.bank_mem_write (bank_mem_write),
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// Dequeue
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.reqq_pop (reqq_pop),
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.reqq_req_st0 (reqq_req_st0),
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.reqq_req_tid_st0 (reqq_req_tid_st0),
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.reqq_req_addr_st0 (reqq_req_addr_st0),
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.reqq_req_writedata_st0(reqq_req_writeword_st0),
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.reqq_req_rd_st0 (reqq_req_rd_st0),
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.reqq_req_wb_st0 (reqq_req_wb_st0),
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.reqq_req_warp_num_st0 (reqq_req_warp_num_st0),
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.reqq_req_mem_read_st0 (reqq_req_mem_read_st0),
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.reqq_req_mem_write_st0(reqq_req_mem_write_st0),
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.reqq_empty (reqq_empty),
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.reqq_full (reqq_full)
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);
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wire mrvq_pop; // Use this
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wire mrvq_full;
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wire mrvq_valid_st0;
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wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] mrvq_tid_st0;
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wire [31:0] mrvq_addr_st0;
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wire [31:0] mrvq_writeword_st0;
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wire [4:0] mrvq_rd_st0;
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wire [1:0] mrvq_wb_st0;
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wire [`NW_M1:0] mrvq_warp_num_st0;
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wire [2:0] mrvq_mem_read_st0;
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wire [2:0] mrvq_mem_write_st0;
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VX_cache_miss_resrv mrvq_queue(
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.clk (clk),
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.reset (reset),
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// Enqueue
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.miss_add (miss_add), // Need to do all
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.miss_add_addr (miss_add_addr),
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.miss_add_data (miss_add_data),
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.miss_add_tid (miss_add_tid),
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.miss_add_rd (miss_add_rd),
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.miss_add_wb (miss_add_wb),
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.miss_add_warp_num (miss_add_warp_num),
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.miss_add_mem_read (miss_add_mem_read),
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.miss_add_mem_write (miss_add_mem_write),
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.miss_resrv_full (mrvq_full)
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// Broadcast
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.is_fill_st1 (is_fill_st1),
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.fill_addr_st1 (addr_st1),
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// Dequeue
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.miss_resrv_pop (mrvq_pop),
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.miss_resrv_valid_st0 (mrvq_valid_st0),
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.miss_resrv_addr_st0 (mrvq_addr_st0),
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.miss_resrv_data_st0 (mrvq_writeword_st0),
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.miss_resrv_tid_st0 (mrvq_tid_st0),
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.miss_resrv_rd_st0 (mrvq_rd_st0),
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.miss_resrv_wb_st0 (mrvq_wb_st0),
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.miss_resrv_warp_num_st0 (mrvq_warp_num_st0),
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.miss_resrv_mem_read_st0 (mrvq_mem_read_st0),
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.miss_resrv_mem_write_st0(mrvq_mem_write_st0)
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);
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wire stall_st0;
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wire stall_st1;
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wire stall_st2;
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assign stall_st1 = stall_st2;
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assign stall_st0 = stall_st1;
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assign dfpq_pop = !dfpq_empty && !stall_st0;
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assign mrvq_pop = !dfpq_pop && mrvq_valid_st0 && !stall_st0;
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assign reqq_pop = !mrvq_pop && reqq_req_st0 && !stall_st0;
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wire qual_is_fill_st0;
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wire qual_valid_st0;
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wire [31:0] qual_addr_st0;
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wire [31:0] qual_writeword_st0;
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wire [`BANK_LINE_SIZE_RNG][31:0] qual_writedata_st0;
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wire [`REQ_INST_META_SIZE-1:0] qual_inst_meta_st0;
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wire is_fill_st1;
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wire valid_st1;
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wire [31:0] addr_st1;
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wire [31:0] writeword_st1;
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wire [`BANK_LINE_SIZE_RNG][31:0] writedata_st1;
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wire [`REQ_INST_META_SIZE-1:0] inst_meta_st1;
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assign qual_is_fill_st0 = dfpq_pop;
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assign qual_valid_st0 = dfpq_pop || mrvq_pop || reqq_pop;
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assign qual_addr_st0 = dfpq_pop ? dfpq_addr_st0 :
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mrvq_pop ? mrvq_addr_st0 :
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reqq_pop ? reqq_req_addr_st0 :
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0;
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assign qual_writeword_st0 = mrvq_pop ? mrvq_writeword_st0 :
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reqq_pop ? reqq_req_writeword_st0 :
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0;
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assign qual_writedata_st0 = dfpq_pop ? dfpq_filldata_st0 : 0;
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assign qual_inst_meta_st0 = mrvq_pop ? {mrvq_rd_st0, mrvq_wb_st0, mrvq_warp_num_st0, mrvq_mem_read_st0, mrvq_mem_write_st0, mrvq_tid_st0} :
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reqq_pop ? {reqq_rd_st0, reqq_wb_st0, reqq_warp_num_st0, reqq_mem_read_st0, reqq_mem_write_st0, reqq_tid_st0} :
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0;
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VX_generic_register #(.N(1)) s0_1 (
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.clk (clk),
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.reset(reset),
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.stall(stall_st1),
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.flush(0),
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.in ({qual_is_fill_st0, qual_valid_st0, qual_addr_st0, qual_writeword_st0, qual_writedata_st0, qual_inst_meta_st0}),
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.out ({is_fill_st1 , valid_st1 , addr_st1 , writeword_st1 , writedata_st1 , inst_meta_st1 })
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);
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endmodule
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