129 lines
3.8 KiB
Verilog
129 lines
3.8 KiB
Verilog
`include "VX_tex_define.vh"
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module VX_tex_addr_gen #(
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parameter CORE_ID = 0,
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parameter REQ_TAG_WIDTH = 1
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) (
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input wire clk,
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input wire reset,
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// handshake
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input wire valid_in,
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output wire ready_in,
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// inputs
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input wire [`NUM_THREADS-1:0] req_tmask,
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input wire [REQ_TAG_WIDTH-1:0] req_tag,
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input wire [`TEX_FILTER_BITS-1:0] filter,
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input wire [`TEX_WRAP_BITS-1:0] wrap_u,
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input wire [`TEX_WRAP_BITS-1:0] wrap_v,
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input wire [`TEX_ADDR_BITS-1:0] base_addr,
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input wire [`TEX_STRIDE_BITS-1:0] log2_stride,
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input wire [`TEX_WIDTH_BITS-1:0] log2_width,
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input wire [`TEX_HEIGHT_BITS-1:0] log2_height,
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input wire [`NUM_THREADS-1:0][31:0] coord_u,
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input wire [`NUM_THREADS-1:0][31:0] coord_v,
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input wire [`NUM_THREADS-1:0][31:0] lod,
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// outputs
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output wire mem_req_valid,
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output wire [`NUM_THREADS-1:0] mem_req_tmask,
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output wire [`TEX_FILTER_BITS-1:0] mem_req_filter,
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output wire [REQ_TAG_WIDTH-1:0] mem_req_tag,
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output wire [`NUM_THREADS-1:0][3:0][31:0] mem_req_addr,
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input wire mem_req_ready
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);
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`UNUSED_PARAM (CORE_ID)
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`UNUSED_VAR (lod)
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wire [`FIXED_FRAC-1:0] u[`NUM_THREADS-1:0][1:0];
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wire [`FIXED_FRAC-1:0] v[`NUM_THREADS-1:0][1:0];
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// addressing mode
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for (genvar i = 0; i < `NUM_THREADS; ++i) begin
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wire [31:0] fu[1:0];
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wire [31:0] fv[1:0];
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assign fu[0] = coord_u[i] - (filter ? (`FIXED_HALF >> log2_width) : 0);
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assign fv[0] = coord_v[i] - (filter ? (`FIXED_HALF >> log2_height) : 0);
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assign fu[1] = coord_u[i] + (filter ? (`FIXED_HALF >> log2_width) : 0);
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assign fv[1] = coord_v[i] + (filter ? (`FIXED_HALF >> log2_height) : 0);
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VX_tex_wrap #(
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.CORE_ID (CORE_ID)
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) tex_wrap_u0 (
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.wrap_i (wrap_u),
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.coord_i (fu[0]),
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.coord_o (u[i][0])
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);
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VX_tex_wrap #(
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.CORE_ID (CORE_ID)
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) tex_wrap_v0 (
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.wrap_i (wrap_v),
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.coord_i (fv[0]),
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.coord_o (v[i][0])
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);
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VX_tex_wrap #(
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.CORE_ID (CORE_ID)
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) tex_wrap_u1 (
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.wrap_i (wrap_u),
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.coord_i (fu[1]),
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.coord_o (u[i][1])
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);
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VX_tex_wrap #(
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.CORE_ID (CORE_ID)
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) tex_wrap_v1 (
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.wrap_i (wrap_v),
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.coord_i (fv[1]),
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.coord_o (v[i][1])
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);
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end
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// addresses generation
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wire [31:0] addr [`NUM_THREADS-1:0][3:0];
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for (genvar i = 0; i < `NUM_THREADS; ++i) begin
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wire [`FIXED_FRAC-1:0] x [1:0];
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wire [`FIXED_FRAC-1:0] y [1:0];
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assign x[0] = u[i][0] >> ((`FIXED_FRAC) - log2_width);
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assign x[1] = u[i][1] >> ((`FIXED_FRAC) - log2_width);
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assign y[0] = v[i][0] >> ((`FIXED_FRAC) - log2_height);
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assign y[1] = v[i][1] >> ((`FIXED_FRAC) - log2_height);
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assign addr [i][0] = base_addr + (x[0] + (y[0] << log2_width)) << log2_stride;
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assign addr [i][1] = base_addr + (x[1] + (y[0] << log2_width)) << log2_stride;
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assign addr [i][2] = base_addr + (x[0] + (y[1] << log2_width)) << log2_stride;
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assign addr [i][3] = base_addr + (x[1] + (y[1] << log2_width)) << log2_stride;
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end
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wire stall_out = mem_req_valid && ~mem_req_ready;
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VX_pipe_register #(
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.DATAW (1 + 4 + `NUM_THREADS * 4 * 32 + REQ_TAG_WIDTH),
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.RESETW (1)
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) pipe_reg (
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.clk (clk),
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.reset (reset),
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.enable (~stall_out),
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.data_in ({valid_in, req_tmask, filter, req_tag, addr}),
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.data_out ({mem_req_valid, mem_req_tmask, mem_req_filter, mem_req_tag, mem_req_addr})
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);
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assign ready_in = ~stall_out;
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endmodule |