27 lines
651 B
Verilog
27 lines
651 B
Verilog
`include "VX_platform.vh"
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module VX_reset_relay #(
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parameter NUM_NODES = 1,
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parameter PASSTHRU = 0
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) (
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input wire clk,
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input wire reset,
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output wire [NUM_NODES-1:0] reset_out
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);
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if (PASSTHRU == 0) begin
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reg [NUM_NODES-1:0] reset_r;
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always @(posedge clk) begin
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for (integer i = 0; i < NUM_NODES; ++i) begin
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reset_r[i] <= reset;
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end
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end
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assign reset_out = reset_r;
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end else begin
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`UNUSED_VAR (clk)
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for (genvar i = 0; i < NUM_NODES; ++i) begin
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assign reset_out[i] = reset;
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end
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end
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endmodule |