33 lines
1.0 KiB
Verilog
33 lines
1.0 KiB
Verilog
`ifndef VX_PERF_MEMSYS_IF
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`define VX_PERF_MEMSYS_IF
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`include "VX_define.vh"
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interface VX_perf_memsys_if ();
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wire [`PERF_CTR_BITS-1:0] icache_reads;
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wire [`PERF_CTR_BITS-1:0] icache_read_misses;
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wire [`PERF_CTR_BITS-1:0] icache_pipe_stalls;
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wire [`PERF_CTR_BITS-1:0] icache_crsp_stalls;
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wire [`PERF_CTR_BITS-1:0] dcache_reads;
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wire [`PERF_CTR_BITS-1:0] dcache_writes;
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wire [`PERF_CTR_BITS-1:0] dcache_read_misses;
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wire [`PERF_CTR_BITS-1:0] dcache_write_misses;
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wire [`PERF_CTR_BITS-1:0] dcache_bank_stalls;
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wire [`PERF_CTR_BITS-1:0] dcache_mshr_stalls;
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wire [`PERF_CTR_BITS-1:0] dcache_pipe_stalls;
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wire [`PERF_CTR_BITS-1:0] dcache_crsp_stalls;
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wire [`PERF_CTR_BITS-1:0] smem_reads;
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wire [`PERF_CTR_BITS-1:0] smem_writes;
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wire [`PERF_CTR_BITS-1:0] smem_bank_stalls;
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wire [`PERF_CTR_BITS-1:0] mem_reads;
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wire [`PERF_CTR_BITS-1:0] mem_writes;
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wire [`PERF_CTR_BITS-1:0] mem_stalls;
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wire [`PERF_CTR_BITS-1:0] mem_latency;
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endinterface
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`endif |