44 lines
1.0 KiB
Verilog
44 lines
1.0 KiB
Verilog
`ifndef VX_COMMIT_IS_IF
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`define VX_COMMIT_IS_IF
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`include "VX_define.vh"
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typedef struct packed {
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logic [`NW_BITS-1:0] warp_num;
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logic [`NUM_THREADS-1:0] thread_mask;
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logic [31:0] curr_PC;
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logic [`NR_BITS-1:0] rd;
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logic rd_is_fp;
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logic wb;
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} is_data_t;
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interface VX_commit_is_if ();
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wire alu_valid;
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wire lsu_valid;
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wire csr_valid;
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wire mul_valid;
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wire fpu_valid;
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wire gpu_valid;
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wire [`ISTAG_BITS-1:0] alu_tag;
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wire [`ISTAG_BITS-1:0] lsu_tag;
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wire [`ISTAG_BITS-1:0] csr_tag;
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wire [`ISTAG_BITS-1:0] mul_tag;
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wire [`ISTAG_BITS-1:0] fpu_tag;
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wire [`ISTAG_BITS-1:0] gpu_tag;
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`IGNORE_WARNINGS_BEGIN
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is_data_t alu_data;
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is_data_t lsu_data;
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is_data_t csr_data;
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is_data_t mul_data;
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is_data_t fpu_data;
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is_data_t gpu_data;
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`IGNORE_WARNINGS_END
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endinterface
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`endif
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