Lingjun Zhu 93531715bb Created a testbench and simulated the read/write of the register file

2019-10-18 22:55:34 -04:00

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cln28hpc/rf2_32x128_wm1

Created a testbench and simulated the read/write of the register file

2019-10-18 22:55:34 -04:00

cln28hpm/rf2_32x128_wm1

Create the memory blocks with CLN28HPM

2019-10-17 15:38:48 -04:00