58 lines
1.8 KiB
Verilog
58 lines
1.8 KiB
Verilog
`include "VX_cache_config.vh"
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module VX_snp_rsp_arb #(
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parameter NUM_BANKS = 1,
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parameter BANK_LINE_SIZE = 1,
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parameter SNP_REQ_TAG_WIDTH = 1
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) (
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input wire clk,
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input wire reset,
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input wire [NUM_BANKS-1:0] per_bank_snp_rsp_valid,
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input wire [NUM_BANKS-1:0][SNP_REQ_TAG_WIDTH-1:0] per_bank_snp_rsp_tag,
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output wire [NUM_BANKS-1:0] per_bank_snp_rsp_ready,
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output wire snp_rsp_valid,
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output wire [SNP_REQ_TAG_WIDTH-1:0] snp_rsp_tag,
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input wire snp_rsp_ready
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);
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if (NUM_BANKS > 1) begin
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wire sel_valid;
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wire [`BANK_BITS-1:0] sel_idx;
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wire [NUM_BANKS-1:0] sel_1hot;
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VX_rr_arbiter #(
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.N(NUM_BANKS)
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) sel_arb (
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.clk (clk),
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.reset (reset),
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.requests (per_bank_snp_rsp_valid),
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.grant_valid (sel_valid),
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.grant_index (sel_idx),
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.grant_onehot(sel_1hot)
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);
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wire stall = ~snp_rsp_ready && snp_rsp_valid;
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VX_generic_register #(
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.N(1 + SNP_REQ_TAG_WIDTH),
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.PASSTHRU(NUM_BANKS <= 2)
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) pipe_reg (
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.clk (clk),
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.reset (reset),
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.stall (stall),
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.flush (1'b0),
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.in ({sel_valid, per_bank_snp_rsp_tag[sel_idx]}),
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.out ({snp_rsp_valid, snp_rsp_tag})
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);
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for (genvar i = 0; i < NUM_BANKS; i++) begin
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assign per_bank_snp_rsp_ready[i] = sel_1hot[i] && !stall;
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end
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end else begin
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assign snp_rsp_valid = per_bank_snp_rsp_valid;
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assign snp_rsp_tag = per_bank_snp_rsp_tag;
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assign per_bank_snp_rsp_ready = snp_rsp_ready;
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end
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endmodule |