62 lines
1.6 KiB
Verilog
62 lines
1.6 KiB
Verilog
`include "VX_platform.vh"
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module VX_opd_collect #(
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parameter INSTW = 1,
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parameter OPDSW = 1,
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parameter PASSTHRU = 0
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) (
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input wire clk,
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input wire reset,
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input wire valid_in,
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output wire ready_in,
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input wire [INSTW-1:0] inst_in,
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input wire [OPDSW-1:0] opds_in,
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output wire [INSTW+OPDSW-1:0] data_out,
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output wire valid_out,
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input wire ready_out
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);
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wire [INSTW-1:0] inst_out;
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wire [OPDSW-1:0] opds_out;
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wire valid_out_tmp, ready_out_tmp;
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VX_skid_buffer #(
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.DATAW (INSTW)
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) skid_buffer (
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.clk (clk),
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.reset (reset),
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.valid_in (valid_in),
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.ready_in (ready_in),
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.data_in (inst_in),
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.data_out (inst_out),
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.valid_out (valid_out_tmp),
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.ready_out (ready_out_tmp)
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);
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VX_gpr_bypass #(
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.DATAW (OPDSW),
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.PASSTHRU (PASSTHRU)
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) gpr_bypass (
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.clk (clk),
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.reset (reset),
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.push (valid_in && ready_in),
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.pop (valid_out_tmp && ready_out_tmp),
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.data_in (opds_in),
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.data_out (opds_out)
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);
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wire stall_out = valid_out && ~ready_out;
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VX_generic_register #(
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.N(1+INSTW+OPDSW)
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) pipe_reg (
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.clk (clk),
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.reset (reset),
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.stall (stall_out),
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.flush (1'b0),
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.in ({valid_out_tmp, inst_out, opds_out}),
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.out ({valid_out, data_out})
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);
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assign ready_out_tmp = ~stall_out;
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endmodule |