d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
47 lines
1.3 KiB
Systemverilog
47 lines
1.3 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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interface VX_sched_csr_if ();
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wire [`PERF_CTR_BITS-1:0] cycles;
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wire [`NUM_WARPS-1:0] active_warps;
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wire [`NUM_WARPS-1:0][`NUM_THREADS-1:0] thread_masks;
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wire alm_empty;
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wire [`NW_WIDTH-1:0] alm_empty_wid;
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wire unlock_warp;
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wire [`NW_WIDTH-1:0] unlock_wid;
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modport master (
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output cycles,
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output active_warps,
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output thread_masks,
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input alm_empty_wid,
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output alm_empty,
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input unlock_wid,
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input unlock_warp
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);
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modport slave (
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input cycles,
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input active_warps,
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input thread_masks,
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output alm_empty_wid,
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input alm_empty,
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output unlock_wid,
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output unlock_warp
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);
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endinterface
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