50 lines
1.5 KiB
Verilog
50 lines
1.5 KiB
Verilog
`include "VX_platform.vh"
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module VX_tex_unit #(
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parameter TADDRW = 32,
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parameter MADDRW = 32,
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parameter DATAW = 32,
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parameter MAXWTW = 8,
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parameter MAXHTW = 8,
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parameter MAXFTW = 2,
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parameter MAXFMW = 1,
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parameter MAXAMW = 2,
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parameter TAGW = 16,
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parameter NUMCRQS = 32
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) (
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input wire clk,
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input wire reset,
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// Texture Request
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input wire tex_req_valid,
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input wire [TADDRW-1:0] tex_req_u,
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input wire [TADDRW-1:0] tex_req_v,
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input wire [MADDRW-1:0] tex_req_addr,
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input wire [MAXWTW-1:0] tex_req_width,
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input wire [MAXHTW-1:0] tex_req_height,
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input wire [MAXFTW-1:0] tex_req_format,
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input wire [MAXFMW-1:0] tex_req_filter,
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input wire [MAXAMW-1:0] tex_req_clamp,
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input wire [TAGW-1:0] tex_req_tag,
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output wire tex_req_ready,
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// Texture Response
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output wire tex_rsp_valid,
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output wire [TAGW-1:0] tex_rsp_tag,
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input wire [DATAW-1:0] tex_rsp_data,
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input wire tex_rsp_ready,
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// Cache Request
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output wire [NUMCRQS-1:0] cache_req_valids,
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output wire [NUMCRQS-1:0][MADDRW-1:0] cache_req_addrs,
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input wire cache_req_ready,
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// Cache Response
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input wire cache_rsp_valid,
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input wire [MADDRW-1:0] cache_rsp_addr,
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input wire [DATAW-1:0] cache_rsp_data,
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output wire cache_rsp_ready
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);
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endmodule |