c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
260 lines
9.9 KiB
Systemverilog
260 lines
9.9 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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`include "VX_fpu_define.vh"
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module VX_fpu_unit import VX_fpu_pkg::*; #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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VX_dispatch_if.slave dispatch_if [`ISSUE_WIDTH],
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VX_fpu_to_csr_if.master fpu_to_csr_if[`NUM_FPU_BLOCKS],
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VX_commit_if.master commit_if [`ISSUE_WIDTH]
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);
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`UNUSED_PARAM (CORE_ID)
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localparam BLOCK_SIZE = `NUM_FPU_BLOCKS;
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localparam NUM_LANES = `NUM_FPU_LANES;
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localparam PID_BITS = `CLOG2(`NUM_THREADS / NUM_LANES);
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localparam PID_WIDTH = `UP(PID_BITS);
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localparam TAG_WIDTH = `LOG2UP(`FPU_REQ_QUEUE_SIZE);
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localparam PARTIAL_BW = (BLOCK_SIZE != `ISSUE_WIDTH) || (NUM_LANES != `NUM_THREADS);
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VX_execute_if #(
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.NUM_LANES (NUM_LANES)
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) execute_if[BLOCK_SIZE]();
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`RESET_RELAY (dispatch_reset, reset);
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VX_dispatch_unit #(
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.BLOCK_SIZE (BLOCK_SIZE),
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.NUM_LANES (NUM_LANES),
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.OUT_REG (PARTIAL_BW ? 1 : 0)
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) dispatch_unit (
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.clk (clk),
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.reset (dispatch_reset),
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.dispatch_if(dispatch_if),
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.execute_if (execute_if)
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);
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VX_commit_if #(
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.NUM_LANES (NUM_LANES)
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) commit_block_if[BLOCK_SIZE]();
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for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin
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`UNUSED_VAR (execute_if[block_idx].data.tid)
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`UNUSED_VAR (execute_if[block_idx].data.wb)
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`UNUSED_VAR (execute_if[block_idx].data.use_PC)
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`UNUSED_VAR (execute_if[block_idx].data.use_imm)
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// Store request info
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wire fpu_req_valid, fpu_req_ready;
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wire fpu_rsp_valid, fpu_rsp_ready;
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wire [NUM_LANES-1:0][`XLEN-1:0] fpu_rsp_result;
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fflags_t fpu_rsp_fflags;
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wire fpu_rsp_has_fflags;
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wire [`UUID_WIDTH-1:0] fpu_rsp_uuid;
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wire [`NW_WIDTH-1:0] fpu_rsp_wid;
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wire [NUM_LANES-1:0] fpu_rsp_tmask;
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wire [`XLEN-1:0] fpu_rsp_PC;
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wire [`NR_BITS-1:0] fpu_rsp_rd;
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wire [PID_WIDTH-1:0] fpu_rsp_pid;
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wire fpu_rsp_sop;
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wire fpu_rsp_eop;
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wire [TAG_WIDTH-1:0] fpu_req_tag, fpu_rsp_tag;
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wire mdata_full;
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wire [`INST_FMT_BITS-1:0] fpu_fmt = execute_if[block_idx].data.imm[`INST_FMT_BITS-1:0];
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wire [`INST_FRM_BITS-1:0] fpu_frm = execute_if[block_idx].data.op_mod[`INST_FRM_BITS-1:0];
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wire execute_fire = execute_if[block_idx].valid && execute_if[block_idx].ready;
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wire fpu_rsp_fire = fpu_rsp_valid && fpu_rsp_ready;
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VX_index_buffer #(
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.DATAW (`UUID_WIDTH + `NW_WIDTH + NUM_LANES + `XLEN + `NR_BITS + PID_WIDTH + 1 + 1),
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.SIZE (`FPU_REQ_QUEUE_SIZE)
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) tag_store (
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.clk (clk),
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.reset (reset),
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.acquire_en (execute_fire),
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.write_addr (fpu_req_tag),
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.write_data ({execute_if[block_idx].data.uuid, execute_if[block_idx].data.wid, execute_if[block_idx].data.tmask, execute_if[block_idx].data.PC, execute_if[block_idx].data.rd, execute_if[block_idx].data.pid, execute_if[block_idx].data.sop, execute_if[block_idx].data.eop}),
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.read_data ({fpu_rsp_uuid, fpu_rsp_wid, fpu_rsp_tmask, fpu_rsp_PC, fpu_rsp_rd, fpu_rsp_pid, fpu_rsp_sop, fpu_rsp_eop}),
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.read_addr (fpu_rsp_tag),
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.release_en (fpu_rsp_fire),
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.full (mdata_full),
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`UNUSED_PIN (empty)
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);
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// resolve dynamic FRM from CSR
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wire [`INST_FRM_BITS-1:0] fpu_req_frm;
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`ASSIGN_BLOCKED_WID (fpu_to_csr_if[block_idx].read_wid, execute_if[block_idx].data.wid, block_idx, `NUM_FPU_BLOCKS)
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assign fpu_req_frm = (execute_if[block_idx].data.op_type != `INST_FPU_MISC
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&& fpu_frm == `INST_FRM_DYN) ? fpu_to_csr_if[block_idx].read_frm : fpu_frm;
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// submit FPU request
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assign fpu_req_valid = execute_if[block_idx].valid && ~mdata_full;
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assign execute_if[block_idx].ready = fpu_req_ready && ~mdata_full;
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`RESET_RELAY (fpu_reset, reset);
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`ifdef FPU_DPI
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VX_fpu_dpi #(
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.NUM_LANES (NUM_LANES),
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.TAGW (TAG_WIDTH),
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.OUT_REG (PARTIAL_BW ? 1 : 3)
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) fpu_dpi (
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.clk (clk),
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.reset (fpu_reset),
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.valid_in (fpu_req_valid),
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.op_type (execute_if[block_idx].data.op_type),
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.lane_mask (execute_if[block_idx].data.tmask),
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.fmt (fpu_fmt),
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.frm (fpu_req_frm),
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.dataa (execute_if[block_idx].data.rs1_data),
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.datab (execute_if[block_idx].data.rs2_data),
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.datac (execute_if[block_idx].data.rs3_data),
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.tag_in (fpu_req_tag),
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.ready_in (fpu_req_ready),
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.valid_out (fpu_rsp_valid),
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.result (fpu_rsp_result),
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.has_fflags (fpu_rsp_has_fflags),
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.fflags (fpu_rsp_fflags),
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.tag_out (fpu_rsp_tag),
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.ready_out (fpu_rsp_ready)
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);
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`elsif FPU_FPNEW
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VX_fpu_fpnew #(
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.NUM_LANES (NUM_LANES),
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.TAGW (TAG_WIDTH),
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.OUT_REG (PARTIAL_BW ? 1 : 3)
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) fpu_fpnew (
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.clk (clk),
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.reset (fpu_reset),
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.valid_in (fpu_req_valid),
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.op_type (execute_if[block_idx].data.op_type),
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.lane_mask (execute_if[block_idx].data.tmask),
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.fmt (fpu_fmt),
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.frm (fpu_req_frm),
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.dataa (execute_if[block_idx].data.rs1_data),
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.datab (execute_if[block_idx].data.rs2_data),
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.datac (execute_if[block_idx].data.rs3_data),
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.tag_in (fpu_req_tag),
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.ready_in (fpu_req_ready),
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.valid_out (fpu_rsp_valid),
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.result (fpu_rsp_result),
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.has_fflags (fpu_rsp_has_fflags),
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.fflags (fpu_rsp_fflags),
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.tag_out (fpu_rsp_tag),
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.ready_out (fpu_rsp_ready)
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);
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`elsif FPU_DSP
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VX_fpu_dsp #(
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.NUM_LANES (NUM_LANES),
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.TAGW (TAG_WIDTH),
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.OUT_REG (PARTIAL_BW ? 1 : 3)
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) fpu_dsp (
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.clk (clk),
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.reset (fpu_reset),
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.valid_in (fpu_req_valid),
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.lane_mask (execute_if[block_idx].data.tmask),
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.op_type (execute_if[block_idx].data.op_type),
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.fmt (fpu_fmt),
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.frm (fpu_req_frm),
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.dataa (execute_if[block_idx].data.rs1_data),
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.datab (execute_if[block_idx].data.rs2_data),
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.datac (execute_if[block_idx].data.rs3_data),
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.tag_in (fpu_req_tag),
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.ready_in (fpu_req_ready),
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.valid_out (fpu_rsp_valid),
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.result (fpu_rsp_result),
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.has_fflags (fpu_rsp_has_fflags),
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.fflags (fpu_rsp_fflags),
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.tag_out (fpu_rsp_tag),
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.ready_out (fpu_rsp_ready)
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);
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`endif
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// handle FPU response
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fflags_t fpu_rsp_fflags_q;
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if (PID_BITS != 0) begin
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fflags_t fpu_rsp_fflags_r;
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always @(posedge clk) begin
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if (reset) begin
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fpu_rsp_fflags_r <= '0;
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end else if (fpu_rsp_fire) begin
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fpu_rsp_fflags_r <= fpu_rsp_eop ? '0 : (fpu_rsp_fflags_r | fpu_rsp_fflags);
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end
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end
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assign fpu_rsp_fflags_q = fpu_rsp_fflags_r | fpu_rsp_fflags;
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end else begin
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assign fpu_rsp_fflags_q = fpu_rsp_fflags;
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end
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assign fpu_to_csr_if[block_idx].write_enable = fpu_rsp_fire && fpu_rsp_eop && fpu_rsp_has_fflags;
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`ASSIGN_BLOCKED_WID (fpu_to_csr_if[block_idx].write_wid, fpu_rsp_wid, block_idx, `NUM_FPU_BLOCKS)
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assign fpu_to_csr_if[block_idx].write_fflags = fpu_rsp_fflags_q;
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// send response
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VX_elastic_buffer #(
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.DATAW (`UUID_WIDTH + `NW_WIDTH + NUM_LANES + `XLEN + `NR_BITS + (NUM_LANES * `XLEN) + PID_WIDTH + 1 + 1),
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.SIZE (0)
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) rsp_buf (
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.clk (clk),
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.reset (reset),
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.valid_in (fpu_rsp_valid),
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.ready_in (fpu_rsp_ready),
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.data_in ({fpu_rsp_uuid, fpu_rsp_wid, fpu_rsp_tmask, fpu_rsp_PC, fpu_rsp_rd, fpu_rsp_result, fpu_rsp_pid, fpu_rsp_sop, fpu_rsp_eop}),
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.data_out ({commit_block_if[block_idx].data.uuid, commit_block_if[block_idx].data.wid, commit_block_if[block_idx].data.tmask, commit_block_if[block_idx].data.PC, commit_block_if[block_idx].data.rd, commit_block_if[block_idx].data.data, commit_block_if[block_idx].data.pid, commit_block_if[block_idx].data.sop, commit_block_if[block_idx].data.eop}),
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.valid_out (commit_block_if[block_idx].valid),
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.ready_out (commit_block_if[block_idx].ready)
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);
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assign commit_block_if[block_idx].data.wb = 1'b1;
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end
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`RESET_RELAY (commit_reset, reset);
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VX_gather_unit #(
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.BLOCK_SIZE (BLOCK_SIZE),
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.NUM_LANES (NUM_LANES),
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.OUT_REG (PARTIAL_BW ? 3 : 0)
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) gather_unit (
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.clk (clk),
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.reset (commit_reset),
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.commit_in_if (commit_block_if),
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.commit_out_if (commit_if)
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);
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endmodule
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