21 lines
559 B
Verilog
21 lines
559 B
Verilog
`ifndef VX_GPU_DRAM_DCACHE_REQ
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`define VX_GPU_DRAM_DCACHE_REQ
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`include "../generic_cache/VX_cache_config.vh"
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interface VX_gpu_dcache_dram_req_if #(
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parameter BANK_LINE_WORDS = 2
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) ();
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// DRAM Request
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wire dram_req_write;
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wire dram_req_read;
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wire [31:0] dram_req_addr;
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wire [BANK_LINE_WORDS-1:0][31:0] dram_req_data;
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wire dram_req_ready;
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wire dram_rsp_ready;
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endinterface
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`endif |