49 lines
1.2 KiB
Verilog
49 lines
1.2 KiB
Verilog
`include "VX_define.vh"
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module VX_issue #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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VX_decode_if decode_if,
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VX_wb_if writeback_if,
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VX_alu_req_if alu_req_if,
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VX_branch_req_if branch_req_if,
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VX_lsu_req_if lsu_req_if,
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VX_csr_req_if csr_req_if,
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VX_mul_req_if mul_req_if,
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VX_gpu_req_if gpu_req_if
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);
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VX_execute_if execute_if();
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VX_scheduler #(
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.CORE_ID(CORE_ID)
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) scheduler (
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.clk (clk),
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.reset (reset),
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.decode_if (decode_if),
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.writeback_if (writeback_if),
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.execute_if (execute_if),
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`UNUSED_PIN (is_empty)
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);
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VX_gpr_stage #(
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.CORE_ID(CORE_ID)
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) gpr_stage (
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.clk (clk),
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.reset (reset),
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.execute_if (execute_if),
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.writeback_if (writeback_if),
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.alu_req_if (alu_req_if),
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.branch_req_if (branch_req_if),
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.lsu_req_if (lsu_req_if),
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.csr_req_if (csr_req_if),
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.mul_req_if (mul_req_if),
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.gpu_req_if (gpu_req_if)
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);
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endmodule |