29 lines
315 B
Verilog
29 lines
315 B
Verilog
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`include "VX_define.v"
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`ifndef VX_ICACHE_RSP
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`define VX_ICACHE_RSP
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interface VX_icache_response_inter ();
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// wire ready;
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// wire stall;
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wire[31:0] instruction;
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// source-side view
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modport snk (
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input instruction
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);
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// source-side view
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modport src (
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output instruction
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);
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endinterface
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`endif |