31 lines
549 B
Systemverilog
31 lines
549 B
Systemverilog
`include "VX_fpu_define.vh"
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module VX_tensor_tb(
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input clk,
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input reset,
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input valid_in,
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input [3:0][1:0][31:0] A_tile,
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input [1:0][3:0][31:0] B_tile,
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input [3:0][3:0][31:0] C_tile,
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output valid_out,
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output [3:0][3:0][31:0] D_tile
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);
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VX_tensor_dpu #() tensor_core (
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.clk(clk),
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.reset(reset),
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.stall(1'b0),
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.valid_in(valid_in),
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.A_tile(A_tile),
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.B_tile(B_tile),
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.C_tile(C_tile),
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.valid_out(valid_out),
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.D_tile(D_tile)
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);
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endmodule
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