112 lines
4.2 KiB
Verilog
112 lines
4.2 KiB
Verilog
`include "VX_define.vh"
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module VX_mem_arb #(
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parameter NUM_REQUESTS = 1,
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parameter DATA_WIDTH = 1,
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parameter TAG_IN_WIDTH = 1,
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parameter TAG_OUT_WIDTH = 1,
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parameter DATA_SIZE = (DATA_WIDTH / 8),
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parameter ADDR_WIDTH = 32 - `CLOG2(DATA_SIZE),
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parameter REQS_BITS = `CLOG2(NUM_REQUESTS)
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) (
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input wire clk,
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input wire reset,
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// input requests
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input wire [NUM_REQUESTS-1:0] req_valid_in,
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input wire [NUM_REQUESTS-1:0][TAG_IN_WIDTH-1:0] req_tag_in,
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input wire [NUM_REQUESTS-1:0][ADDR_WIDTH-1:0] req_addr_in,
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input wire [NUM_REQUESTS-1:0] req_rw_in,
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input wire [NUM_REQUESTS-1:0][DATA_SIZE-1:0] req_byteen_in,
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input wire [NUM_REQUESTS-1:0][DATA_WIDTH-1:0] req_data_in,
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output wire [NUM_REQUESTS-1:0] req_ready_in,
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// input response
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output wire [NUM_REQUESTS-1:0] rsp_valid_out,
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output wire [NUM_REQUESTS-1:0][TAG_IN_WIDTH-1:0] rsp_tag_out,
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output wire [NUM_REQUESTS-1:0][DATA_WIDTH-1:0] rsp_data_out,
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input wire [NUM_REQUESTS-1:0] rsp_ready_out,
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// output request
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output wire req_valid_out,
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output wire [TAG_OUT_WIDTH-1:0] req_tag_out,
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output wire [ADDR_WIDTH-1:0] req_addr_out,
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output wire req_rw_out,
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output wire [DATA_SIZE-1:0] req_byteen_out,
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output wire [DATA_WIDTH-1:0] req_data_out,
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input wire req_ready_out,
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// output response
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input wire rsp_valid_in,
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input wire [TAG_OUT_WIDTH-1:0] rsp_tag_in,
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input wire [DATA_WIDTH-1:0] rsp_data_in,
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output wire rsp_ready_in
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);
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if (NUM_REQUESTS > 1) begin
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wire [REQS_BITS-1:0] req_idx;
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wire [NUM_REQUESTS-1:0] req_1hot;
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VX_rr_arbiter #(
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.N(NUM_REQUESTS)
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) req_arb (
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.clk (clk),
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.reset (reset),
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.requests (req_valid_in),
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`UNUSED_PIN (grant_valid),
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.grant_index (req_idx),
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.grant_onehot (req_1hot)
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);
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wire stall = ~req_ready_out && req_valid_out;
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VX_generic_register #(
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.N(1 + TAG_OUT_WIDTH + ADDR_WIDTH + 1 + DATA_SIZE + DATA_WIDTH),
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.PASSTHRU(NUM_REQUESTS <= 2)
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) pipe_reg (
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.clk (clk),
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.reset (reset),
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.stall (stall),
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.flush (1'b0),
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.in ({req_valid_in[req_idx], {req_tag_in[req_idx], REQS_BITS'(req_idx)}, req_addr_in[req_idx], req_rw_in[req_idx], req_byteen_in[req_idx], req_data_in[req_idx]}),
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.out ({req_valid_out, req_tag_out, req_addr_out, req_rw_out, req_byteen_out, req_data_out})
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);
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for (genvar i = 0; i < NUM_REQUESTS; i++) begin
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assign req_ready_in[i] = req_1hot[i] && ~stall;
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end
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///////////////////////////////////////////////////////////////////////
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wire [REQS_BITS-1:0] rsp_sel = rsp_tag_in[REQS_BITS-1:0];
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for (genvar i = 0; i < NUM_REQUESTS; i++) begin
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assign rsp_valid_out[i] = rsp_valid_in && (rsp_sel == REQS_BITS'(i));
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assign rsp_tag_out[i] = rsp_tag_in[REQS_BITS +: TAG_IN_WIDTH];
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assign rsp_data_out[i] = rsp_data_in;
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end
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assign rsp_ready_in = rsp_ready_out[rsp_sel];
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end else begin
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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assign req_valid_out = req_valid_in;
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assign req_tag_out = req_tag_in;
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assign req_addr_out = req_addr_in;
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assign req_rw_out = req_rw_in;
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assign req_byteen_out = req_byteen_in;
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assign req_data_out = req_data_in;
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assign req_ready_in = req_ready_out;
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assign rsp_valid_out = rsp_valid_in;
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assign rsp_tag_out = rsp_tag_in;
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assign rsp_data_out = rsp_data_in;
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assign rsp_ready_in = rsp_ready_out;
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end
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endmodule |