33 lines
670 B
Verilog
33 lines
670 B
Verilog
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`ifndef VX_WARP_CTL_INTER
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`define VX_WARP_CTL_INTER
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`include "../VX_define.vh"
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interface VX_warp_ctl_inter ();
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wire[`NW_BITS-1:0] warp_num;
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wire change_mask;
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wire[`NUM_THREADS-1:0] thread_mask;
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wire wspawn;
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wire[31:0] wspawn_pc;
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wire[`NUM_WARPS-1:0] wspawn_new_active;
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wire ebreak;
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// barrier
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wire is_barrier;
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wire[31:0] barrier_id;
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wire[$clog2(`NUM_WARPS):0] num_warps;
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wire is_split;
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wire dont_split;
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wire[`NW_BITS-1:0] split_warp_num;
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wire[`NUM_THREADS-1:0] split_new_mask;
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wire[`NUM_THREADS-1:0] split_later_mask;
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wire[31:0] split_save_pc;
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endinterface
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`endif |