19 lines
367 B
Verilog
19 lines
367 B
Verilog
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`ifndef VX_MW_WB_INTER
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`define VX_MW_WB_INTER
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`include "../VX_define.vh"
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interface VX_mw_wb_inter ();
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wire[`NUM_THREADS-1:0][31:0] alu_result;
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wire[`NUM_THREADS-1:0][31:0] mem_result;
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wire[4:0] rd;
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wire[1:0] wb;
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wire[31:0] PC_next;
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wire[`NUM_THREADS-1:0] valid;
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wire [`NW_BITS-1:0] warp_num;
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endinterface
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`endif |