32 lines
684 B
Verilog
32 lines
684 B
Verilog
`include "VX_define.vh"
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module VX_priority_encoder_w_mask
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#(
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parameter N = 10
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)
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(
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input wire[N-1:0] valids,
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output reg [N-1:0] mask,
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//output reg[$clog2(N)-1:0] index,
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output reg[(`LOG2UP(N))-1:0] index,
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//output reg[`LOG2UP(N):0] index, // eh
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output reg found
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);
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integer i;
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always @(valids) begin
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index = 0;
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found = 0;
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// mask = 0;
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for (i = 0; i < N; i=i+1) begin
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if (valids[i]) begin
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//index = i[$clog2(N)-1:0];
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index = i[(`LOG2UP(N))-1:0];
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found = 1;
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// mask[index] = (1 << i);
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// $display("%h",(1 << i));
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end
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end
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end
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assign mask = found ? (1 << index) : 0;
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endmodule |