40 lines
938 B
Verilog
40 lines
938 B
Verilog
`include "VX_platform.vh"
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`include "VX_define.vh"
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module VX_tex_pt_addr #(
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parameter FRAC_BITS = 20,
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parameter INT_BITS = 32 - FRAC_BITS
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) (
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input wire clk,
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input wire reset,
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input wire valid_in,
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output wire ready_out,
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input wire [`CSR_WIDTH-1:0] tex_addr,
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input wire [`CSR_WIDTH-1:0] tex_width,
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input wire [`CSR_WIDTH-1:0] tex_height,
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input wire [31:0] tex_u,
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input wire [31:0] tex_v,
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output wire [31:0] pt_addr,
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output wire valid_out,
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input wire ready_in
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);
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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reg [31:0] x_offset;
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reg [31:0] y_offset;
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assign x_offset = tex_u >> (32'(FRAC_BITS) - tex_width);
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assign y_offset = tex_v >> (32'(FRAC_BITS) - tex_height);
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assign pt_addr = (tex_addr << (32 - `CSR_WIDTH)) + x_offset + (y_offset << tex_width);
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assign valid_out = valid_in;
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assign ready_out = ready_in;
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endmodule |